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International Conference on Mechanical, Control and computer Engineering (ICMCCE)

作者： Yuan Liang Longxiang Yin Ning Xu School of Computer Science and Technology Wuhan University of Technology Wuhan China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Information Engineering Wuhan University of Technology Wuhan China

Conventional reconfigurable architectures, e.g., Field-Programmable Gate Array (FPGA), are confronted with the inflexibility of the on-chip local memory architecture and the scarce memory resource, which result in the inflexibility to deal with the current memory-thirsty data-intensive applications. Emerging nonvolatile devices, such as resistive random-access memory (RRAM), can operate in a logic-in-memory way, i.e., they can act as both a nonvolatile memory element and a switch, and thus, have the potential to provide higher flexibility and data processing ability. We propose a field-programmable logic-in-memory architecture based on RRAM technology, which is a two-dimensional tile array, where each tile is an RRAM-based crossbar array and can be remolded into three basic modes including logic, interconnect and memory. We further develop a specific adaptive algorithm for placement and routing, which can well exploit the logic-in-memory architecture characteristics. Comparing with traditional FPGAs, our architecture shows 1.9x lower power consumption, 2.8x lower delay, and 5.6x higher performance.

关键词： Nonvolatile memory computer architecture Switches Routing Delays system-on-chip Reconfigurable architectures

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Energy-Constrained Task Scheduling in Heterogeneous Distributed systems

Energy-Constrained Task Scheduling in Heterogeneous Distribu...

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International Conference on computer Supported Cooperative Work in Design

作者： Chen Chen Jie Zhu Haiping Huang Yingmeng Gao Nanjing University of Posts & Telecommunications Nanjing China State Key Laboratory Chinese of Computer Architecture Institute of Computing Technology Academy of Sciences Beijing China Jiangsu High Technology Research Key Laboratory for Wireless Sensor Networks Nanjing China

The resource-constrained task scheduling problem has been one of the popular research topics in cloud computing systems. By employing the dynamic voltage and frequency scaling (DVFS) techniques, the task scheduling can be further constrained by energy consumption. The paper investigates the DAG task scheduling considering both the resource and energy constraints in heterogeneous distributed systems. The objective is to minimize the scheduling length. An energy-constrained task scheduling framework is employed, where tasks are initially scheduled according to their upward rank values. Then two heuristics are proposed to improve the initial solution, namely, the simulated annealing local search method and the frequency adjustment method. Experiments are conducted by testing a large number of instances with multiple parameter settings, and the results show that the proposed algorithms are effective and efficient.

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In-Field Testing of NAND Flash Storage: Why and How?

In-Field Testing of NAND Flash Storage: Why and How?

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Asian Test Symposium (ATS)

作者： Yu Hu Xinli Gu Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China North America Network Division Huawei Technologies Company Limited Santa Clara USA

NAND Flash memories have rapidly emerged as a storage class memory such as SSD (Solid State Disk), CF (Compact Flash) Card, SD (Secure Digital Memory) Card. Due to its distinct operation mechanisms, NAND Flash memory suffers from erase/program endurance, data retention and program/read disturbance problems. Specifically, erase and program operation keeps in developing bad blocks during the lifetime of memory chips. Bad blocks are blocks that contain faulty bits but the ECC (Error Correction Code) algorithm cannot correct them. Although wear leveling tries to balance the erase/program operations on different blocks so that all blocks can wear out at a similar pace, new bad blocks still inevitably *** propose an in-field testing technique which takes some pages in a block as predictors. Due to wear out faster than the other pages, the predictors will become bad before the other pages in the block become bad. The further questions are (1) how to detect those wearing fast pages so as to use them as predictors, (2) how many predictors are needed to achieve a satisfactory prediction accuracy, (3) misprediction will result in what negative impact on performance and endurance.

关键词： Flash memory Error correction codes Laboratories computer architecture North America computers

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Scaling Up the IFDS Algorithm with Efficient Disk-Assisted computing

Scaling Up the IFDS Algorithm with Efficient Disk-Assisted C...

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International Symposium on Code Generation and Optimization (CGO)

作者： Haofeng Li Haining Meng Hengjie Zheng Liqing Cao Jie Lu Lian Li Lin Gao University of Chinese Academy of Sciences Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China TianqiSoft Inc China

ISBN: (数字)9781728186139

ISBN: (纸本)9781728186146

The IFDS algorithm can be memory-intensive, requiring a memory budget of more than 100 GB of RAM for some applications. The large memory requirements significantly restrict the deployment of IFDS-based tools in practise. To improve this, we propose a disk-assisted solution that drastically reduces the memory requirements of traditional IFDS solvers. Our solution saves memory by 1) recomputing instead of memorizing intermediate analysis data, and 2) swapping in-memory data to disk when memory usages reach a threshold. We implement sophisticated scheduling schemes to swap data between memory and disks efficiently. We have developed a new taint analysis tool, DiskDroid, based on our disk-assisted IFDS solver. Compared to FlowDroid, a state-of-the-art IFDS-based taint analysis tool, for a set of 19 apps which take from 10 to 128 GB of RAM by FlowDroid, DiskDroid can analyze them with less than 10GB of RAM at a slight performance improvement of 8.6%. In addition, for 21 apps requiring more than 128GB of RAM by FlowDroid, DiskDroid can analyze each app in 3 hours, under the same memory budget of 10GB. This makes the tool deployable to normal desktop environments. We make the tool publicly available at https://***/HaofLi/DiskDroid.

关键词： Scalability Memory management Random access memory Tools Optimization

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An ultrasound system for tumor detection in soft tissues using low transient pulse

An ultrasound system for tumor detection in soft tissues usi...

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IEEE International Conference on Automation Science and Engineering (CASE)

作者： Ashish R. Ratnakar MengChu Zhou Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA MoE Key Laboratory of Embedded System and Service Computing Tongji University Shanghai China

This work presents a method to detect the size and location of tumor in soft tissues using ultrasound. Quantitative ultrasound is utilized to allow an ultrasound signal to be sent from a transmitter to multiple receivers. This received signal is analyzed for echogenic and echolucent tumors to differentiate between the two along with non-tumor sample and also studied for the delay to determine the size/location of the tumor. The proposed system utilizes Low Transient Pulse (LTP) technique and is implemented using Field Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) technologies. In this co-design architecture, DSP carries out the analysis of received demodulated signal at a lower speed while FPGA runs at a higher one to generate LTP signal and demodulate bandpass ultrasonic signal. This work elaborates the implementation of Quadrature Amplitude Modulation (QAM) receiver on FPGA for the received signal from an ultrasound detector. LTP is applied to the tumor samples through the transmitter and the received signal at an ultrasonic receiver is passed through QAM to obtain different maxima that are then further used to compute the location and the size of the tumor using DSP. This dual platform co-design demonstrates a good application of a FPGA/DSP platform for the LTP generation and received signal processing.

关键词： Digital signal processing Field programmable gate arrays Tumors Ultrasonic imaging Clocks Quadrature amplitude modulation Receivers

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Variation Enhanced Attacks Against RRAM-based Neuromorphic computing system

arXiv

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arXiv 2023年

作者： Lv, Hao Li, Bing Zhang, Lei Liu, Cheng Wang, Ying Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China State Key Laboratory of Computer Architecture China Capital Normal University China

The RRAM-based neuromorphic computing system (NCS) has amassed explosive interests for its superior data processing capability and energy efficiency than traditional architectures, and thus being widely used in many data-centric applications. The reliability and security issues of the NCS therefore become an essential problem. In this paper, we systematically investigated the adversarial threats to the RRAM-based NCS and observed that the RRAM hardware feature can be leveraged to strengthen the attack effect, which hasn't been granted sufficient attention by previous algorithmic attack methods. Thus, we proposed two types of hardware-aware attack methods with respect to different attack scenarios and objectives. The first is adversarial attack, VADER, which perturbs the input samples to mislead the prediction of neural networks. The second is fault injection attack, EFI, which perturbs the network parameter space such that a specified sample will be classified to a target label, while maintaining the prediction accuracy on other samples. Both attack methods leverage the RRAM properties to improve the performance compared with the conventional attack methods. Experimental results show that our hardware-aware attack methods can achieve nearly 100% attack success rate with extremely low operational cost, while maintaining the attack stealthiness. Copyright © 2023, The Authors. All rights reserved.

关键词： RRAM

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Poseidon: Practical Homomorphic Encryption Accelerator

Poseidon: Practical Homomorphic Encryption Accelerator

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IEEE Symposium on High-Performance computer architecture

作者： Yinghao Yang Huaizhi Zhang Shengyu Fan Hang Lu Mingzhe Zhang Xiaowei Li State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China State Key Laboratory of Information Security Institute of Information Engineering CAS Beijing China Zhongguancun Laboratory Beijing China

With the development of the important solution for privacy computing, the explosion of data size and computing intensity in Fully Homomorphic Encryption (FHE) has brought enormous challenges to the hardware design. In this paper, we propose a practical FHE accelerator - "Poseidon", which focuses on improving the hardware resource and bandwidth consumption. Poseidon supports complex FHE operations like Bootstrapping, keyswitch, Rotation and so on, under limited FPGA resources. It refines these operations by abstracting five key operators: Modular Addition (MA), Modular Multiplication (MM), Number Theoretic Transformation (NTT), Automorphsim and Shared Barret Reduction (SBT). These operators are combined and reused to implement higher-level FHE operations. To utilize the FPGA resources more efficiently and improve the parallelism, we adopt the radix-based NTT algorithm and propose HFAuto, an optimized automorphism implementation suitable for FPGA. Then, we design the hardware accelerator based on the optimized key operators and HBM to maximize computational efficiency. We evaluate Poseidon with four domain-specific FHE benchmarks on Xilinx Alveo U280 FPGA. Empirical results show that the efficient reuse of the operator cores and on-chip storage enables superior performance compared with the state-of-the-art GPU, FPGA and accelerator ASICs. We highlight the following results: (1) up to 370× speedup over CPU for the basic operations of FHE; (2) up to 1300×/52× speedup over CPU and the FPGA solution for the key operators; (3) up to 10.6×/8.7× speedup over GPU and the ASIC solution for the FHE benchmark.

关键词： Data privacy Graphics processing units Bandwidth Benchmark testing Parallel processing Explosions system-on-chip

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Improved condition for controllability of strongly dependent strict minimal siphons in Petri nets

Improved condition for controllability of strongly dependent...

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IEEE International Conference on Networking, Sensing and Control

作者： GuanJun Liu ChangJun Jiang MengChu Zhou Key Laboratory of the MoE for Embedded System and Service Computing University of Tongji Shanghai China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ USA

Li and Zhou propose an important concept for Petri nets: elementary siphons. They partition siphons into elementary and dependent ones. The controllability of the latter can be ensured by the former's proper control. They give a sufficient condition to decide whether a dependent siphon is controlled by its elementary ones in S 3 PR. However, this condition is so loose that in many cases the controllability of a dependent SMS cannot be determined although it is actually controlled. In this paper, we propose an improved condition to decide the controllability of strongly dependent SMS.

关键词： Controllability system recovery Nickel Flexible manufacturing systems Petri nets Sufficient conditions Control theory

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ArchRanker: A Ranking Approach to Design Space Exploration 14

ArchRanker: A Ranking Approach to Design Space Exploration

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ACM/IEEE International Symposium on computer architecture

作者： Tianshi Chen Qi Guo Ke Tang Olivier Temam Zhiwei Xu Zhi-Hua Zhou Yunji Chen State Key Laboratory of Computer Architecture Institute of Computing Technology (ICT) CAS China Carnegie Mellon University United States University of Science and Technology of China China Inria France National Key Laboratory for Novel Software Technology Nanjing University China

ISBN: (纸本)9781479943944

Architectural Design Space Exploration (DSE) is a notoriously difficult problem due to the exponentially large size of the design space and long simulation times. Previously, many studies proposed to formulate DSE as a regression problem which predicts architecture responses (e.g., time, power) of a given architectural configuration. Several of these techniques achieve high accuracy, though often at the cost of significant simulation time for training the regression models. We argue that the information the architect mostly needs during the DSE process is whether a given configuration will perform better than another one in the presences of design constraints, or better than any other one seen so far, rather than precisely estimating the performance of that configuration. Based on this observation, we propose a novel ranking-based approach to DSE where we train a model to predict which of two architecture configurations will perform best. We show that, not only this ranking model more accurately predicts the relative merit of two architecture configurations than an ANN-based state-of-the-art regression model, but also that it requires much fewer training simulations to achieve the same accuracy, or that it can be used for and is even better at quantifying the performance gap between two configurations. We implement the framework for training and using this model, called ArchRanker, and we evaluate it on several DSE scenarios (unicore/multicore design spaces, and both time and power performance metrics). We try to emulate as closely as possible the DSE process by creating constraint-based scenarios, or an iterative DSE process. We find that ArchRanker makes 29.68% to 54.43 % fewer incorrect predictions on pair-wise relative merit of configurations (tested with 79,800 configuration pairs) than an ANN-based regression model across all DSE scenarios considered (values averaged over all benchmarks for each scenario). We also find that, to achieve the same accuracy as Arc

关键词： Design DSE training

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RISC-NN: Use RISC, NOT CISC as Neural Network Hardware Infrastructure

arXiv

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arXiv 2021年

作者： Xiang, Taoran Zhang, Lunkai An, Shuqian Ye, Xiaochun Zhang, Mingzhe Liu, Yanhuan Yan, Mingyu Wang, Da Zhang, Hao Li, Wenming Sun, Ninghui Fan, Dongrui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing100190 China

Neural Networks (NN) have been proven to be powerful tools to analyze Big Data. However, traditional CPUs cannot achieve the desired performance and/or energy efficiency for NN applications. Therefore, numerous NN accelerators have been used or designed to meet these goals. These accelerators all fall into three categories: GPGPUs, ASIC NN Accelerators and CISC NN Accelerators. GPGPUs achieve general purpose and high computing throughput, but cannot provide desired energy efficiency because their stream architecture cannot achieve efficient data reuse required by NN applications. ASIC NN Accelerators achieve best performance or energy efficiency through advanced data reuse optimization, however, they only support limited NN use cases. CISC NN Accelerators aim to achieve both general purpose and high energy efficiency by decomposing NN applications into multiple relatively simple matrix or vector CISC instructions. Though CISC NN Accelerators can achieve considerable smaller memory footprint than GPGPU thus improve energy efficiency;they still fail to provide same level of data reuse optimization achieved by ASIC NN Accelerators because of the inherited poor pragrammability of their CISC architecture. We argue that, for NN Accelerators, RISC is a better design choice than CISC, as is the case with general purpose processors. We propose RISC-NN, a novel many-core RISC-based NN accelerator that achieves high expressiveness and high parallelism and features strong programmability and low control-hardware costs. We show that, RISC-NN can implement all the necessary instructions of state-of-the-art CISC NN Accelerators;in the meantime, RISC-NN manages to achieve advanced optimization such as multiple-level data reuse and support for Sparse NN applications which previously only existed in ASIC NN Accelerators. Experiment results show that, RISC-NN achieves on average 11.88× performance efficiency compared with state-of-the-art Nvidia TITAN Xp GPGPU for various NN applicati

关键词： Acceleration

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