In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5...
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Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of ...
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Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.
In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation...
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In this paper, we focus on generation of a universal path candidate set V that contains testable long paths for delay testing. Some strategies are presented to speed up the depth first search procedure of U generation, targeting the reduction of sensitization criteria checking times. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth first search approach.
In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and ...
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In this paper, an automatic test instruction generation (ATIG) technique using expanded instructions is presented for software-based selftesting (SBST) of processors. First, mappings between expanded instructions and signals are obtained through data mining, and they are used to impose value ranges of expanded instructions on component signals and generate instruction-level constraints. Second, virtual circuits are established based on the instruction-level constraints, and test patterns are generated for the constrained components. Third, test patterns are translated into test instructions according to the values of controlling signals and constraints for their mappings to instructions, and an SBST program is produced after assembling the test instructions. Experimental results on the Parwan processor show that the proposed ATIG technique can achieve 94.8％ stuck-at fault coverage, which is close to that of the full-scan test generation method. In addition, it can cut down 57％ test volume of the previous random pattern generation based SBST technique, while the test time reduces to one thirteenth of the previous SBST technique.
As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimu...
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As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.
Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testabi...
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Modern compilers use machine learning to find from their prior experience useful heuristics for new programs encountered in order to accelerate the optimization process. However, prior experience might not be applicab...
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A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardwa...
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This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machine...
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This paper presents a new approach to reduce finite state machines with respect to a CTL formula to alleviate state explosion problem. Reduction is achieved by removing parts useless to the formula of original machines. The main contribution of this paper is to exploit relations among subformulas of the CTL formula so as to gain more reduction, as well as to extend traditional pruning method, which handles only existential formulas, to handle universal formulas. Based on this kind of reduction, verification of a large system, which usually consists of several components, can be done by evaluating properties on a reduced version of the system, which is built by composing components of the system one by one while doing reduction after each composition. Experimental results show the effectiveness of the approach. Especially when a property is written in a more detailed way, that is to describe the system part by part, the approach has a great potential.
As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study...
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