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Symposium of Image, Signal Processing, and Artificial Vision (STSIVA)

作者： Chang Lu Dayu Feng Jie Zhu Haiping Huang Nanjing University of Posts & Telecommunications Nanjing China Jiangsu Key Laboratory of Big Data Security & Intelligent Processing Nanjing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Jiangsu High Technology Research Key Laboratory for Wireless Sensor Networks Nanjing China

ISBN: (纸本)9781665426565

As a NP-hard problem, it is always baffling to figure out a scheduling strategy to arrange the interconnected tasks of a workflow on the infinite number of resources in the cloud environment so that the workflow can be addressed efficiently and robustly. This paper focuses on scheduling the workflow’s tasks on the cloud resources with less rental cost of resources while the whole schedule length (makespan) will not exceed the given deadline. As one of the most popular evolutionary algorithms, particle swarm optimization (PSO) has been successfully applied for the workflow scheduling problem. Inspired by the idea of multiple groups and the distributed parallel computing, we develop an enhanced PSO algorithm for the workflow scheduling problem in clouds. Besides, a pretreatment strategy is adopted to simplify the workflow’s structure. The experimental results demonstrate that our proposal has good performance on improving the algorithm’s searching ability and finding better solutions.

关键词： Schedules Costs Processor scheduling NP-hard problem Parallel processing Scheduling Proposals

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AutoQNN: An End-to-End Framework for Automatically Quantizing Neural Networks

arXiv

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arXiv 2023年

作者： Gong, Cheng Lu, Ye Dai, Surong Qian, Deng Du, Chenkun Li, Tao College of Software Nankai University Tianjin300350 China College of Computer Science Nankai University Tianjin300350 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

Exploring the expected quantizing scheme with suitable mixed-precision policy is the key point to compress deep neural networks (DNNs) in high efficiency and accuracy. This exploration implies heavy workloads for domain experts, and an automatic compression method is needed. However, the huge search space of the automatic method introduces plenty of computing budgets that make the automatic process challenging to be applied in real scenarios. In this paper, we propose an end-to-end framework named AutoQNN, for automatically quantizing different layers utilizing different schemes and bitwidths without any human labor. AutoQNN can seek desirable quantizing schemes and mixed-precision policies for mainstream DNN models efficiently by involving three techniques: quantizing scheme search (QSS), quantizing precision learning (QPL), and quantized architecture generation (QAG). QSS introduces five quantizing schemes and defines three new schemes as a candidate set for scheme search, and then uses the differentiable neural architecture search (DNAS) algorithm to seek the layer- or model-desired scheme from the set. QPL is the first method to learn mixed-precision policies by reparameterizing the bitwidths of quantizing schemes, to the best of our knowledge. QPL optimizes both classification loss and precision loss of DNNs efficiently and obtains the relatively optimal mixed-precision model within limited model size and memory footprint. QAG is designed to convert arbitrary architectures into corresponding quantized ones without manual intervention, to facilitate end-to-end neural network quantization. We have implemented AutoQNN and integrated it into Keras. Extensive experiments demonstrate that AutoQNN can consistently outperform state-of-the-art quantization. For 2-bit weight and activation of AlexNet and ResNet18, AutoQNN can achieve the accuracy results of 59.75% and 68.86%, respectively, and obtain accuracy improvements by up to 1.65% and 1.74%, respectively, compared

关键词： Deep neural networks

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Fingerprint Presentation Attack Detector Using Global-Local Model

arXiv

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arXiv 2024年

作者： Liu, Haozhe Zhang, Wentian Liu, Feng Wu, Haoqian Shen, Linlin The Computer Vision Institute College of Computer Science and Software Engineering SZU Branch Shenzhen Institute of Artificial Intelligence and Robotics for Society The National Engineering Laboratory for Big Data System Computing Technology The Guangdong Key Laboratory of Intelligent Information Processing Shenzhen University Shenzhen518060 China

The vulnerability of automated fingerprint recognition systems (AFRSs) to presentation attacks (PAs) promotes the vigorous development of PA detection (PAD) technology. However, PAD methods have been limited by information loss and poor generalization ability, resulting in new PA materials and fingerprint sensors. This paper thus proposes a global-local model-based PAD (RTK-PAD) method to overcome those limitations to some extent. The proposed method consists of three modules, called: 1) the global module;2) the local module;and 3) the rethinking module. By adopting the cut-out-based global module, a global spoofness score predicted from nonlocal features of the entire fingerprint images can be achieved. While by using the texture in-painting-based local module, a local spoofness score predicted from fingerprint patches is obtained. The two modules are not independent but connected through our proposed rethinking module by localizing two discriminative patches for the local module based on the global spoofness score. Finally, the fusion spoofness score by averaging the global and local spoofness scores is used for PAD. Our experimental results evaluated on LivDet 2017 show that the proposed RTK-PAD can achieve an average classification error (ACE) of 2.28% and a true detection rate (TDR) of 91.19% when the false detection rate (FDR) equals 1.0%, which significantly outperformed the state-of-the-art methods by ∼10% in terms of TDR (91.19% versus 80.74%). Copyright © 2024, The Authors. All rights reserved.

关键词： Supervised learning

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A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS

A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with inp...

引用

28th IEEE Symposium on VLSI Circuits, VLSIC 2014

作者： Li, Hao Chen, Shuai Yang, Liqiong Bai, Rui Hu, Weiwu Zhong, Freeman Y. Palermo, Samuel Chiang, Patrick Yin School of Electrical Engineering and Computer Science Oregon State University Corvallis OR 97331 United States Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Texas A and M University College Station TX 77843 United States State Key Laboratory of ASIC and System Fudan University Shanghai 200433 China LSI Corporation San Jose CA 95131 United States

ISBN: (纸本)9781479933273

A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER-12, achieves a 1MHz phase tracking bandwidth, tolerates ±50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at V DD=0.8V. © 2014 IEEE.

关键词： Clocks

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Design of a flip-flop circuit within digital logic analyzer based on FPGA

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Harbin Gongye Daxue Xuebao/Journal of Harbin institute of technology 2009年第SUPPL. 1期41卷 58-62页

作者： Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.

关键词： Field programmable gate arrays (FPGA)

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A benchmark of ocular disease intelligent recognition: One shot for Multi-disease detection

arXiv

引用

arXiv 2021年

作者： Li, Ning Li, Tao Hu, Chunyu Wang, Kai Kang, Hong College of Computer Science Nankai university Tianjin300350 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Science Beijing100190 China Beijing Shanggong Medical Technology Co. Ltd Beijing100176 China

In ophthalmology, early fundus screening is an economic and effective way to prevent blindness caused by ophthalmic diseases. Clinically, due to the lack of medical resources, manual diagnosis is time-consuming and may delay the condition. With the development of deep learning, some researches on ophthalmic diseases have achieved good results, however, most of them are just based on one disease. During fundus screening, ophthalmologists usually give diagnoses of multi-disease on binocular fundus image, so we release a dataset with 8 diseases to meet the real medical scene, which contains 10,000 fundus images from both eyes of 5,000 patients. We did some benchmark experiments on it through some state-of-the-art deep neural networks. We found simply increasing the scale of network cannot bring good results for multi-disease classification, and a well-structured feature fusion method combines characteristics of multi-disease is needed. Through this work, we hope to advance the research of related fields. Copyright © 2021, The Authors. All rights reserved.

关键词： computer aided diagnosis

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Parallelization of LU decomposition on the godson-Tv1 many-core architecture

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Jisuanji Xuebao/Chinese Journal of computers 2009年第11期32卷 2157-2167页

作者： Long, Guo-Ping Fan, Dong-Rui Key Laboratory of Computer Systems and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

The many-core architecture is increasingly becoming a promising computing platform due to the advancement of semi-conductor technology. LU decomposition is a widely used kernel in both scientific and engineering computations. Although there are a lot of related works on traditional parallel architectures, there is still little work focusing on parallelizing it on many-core architectures. This paper investigates this problem from three aspects: load balancing, latency hiding and performance modeling. There are three contributions of this work: Firstly, a novel load balancing technique has been introduced to overcome the limitations of 2D scatter decomposition. Experimental results show that the proposed scheme achieves 20% performance improvement without optimization and 40% improvement after optimization. Secondly, an analytical performance model is presented. Quantitative experimental study shows that by carefully hiding memory latency through on chip memory hierarchy and for a selected block size, the upper bound of theoretical performance can be approximated by experiments. Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.

关键词： Parallel architectures

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Conceptual model of real-time IoT systems

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Frontiers of Information technology & Electronic Engineering 2019年第11期20卷 1457-1464页

作者： Bo YUAN De-ji CHEN Dong-mei XU Ming CHEN Department of Computer Science and Technology Tongji UniversityShanghai 201804China School of Electronics and Information Engineering Jinggangshan UniversityJi'an 343009China MOE Key Laboratory of Embedded System and Service Computing Tongji UniversityShanghai 201804China China Electronics Standardization Institute Beijing 100007China Chinesisch-Deutsche Hochschule for Angewandte Wissenschaften Tongji UniversityShanghai 201804China

We address a special kind of Internet of Things (IoT) systems that are also real-time. We call them real-time IoT (RT-IoT) systems. An RT-IoT system needs to meet timing constraints of system delay, clock synchronization, deadline, and so on. The timing constraints turn to be more stringent as we get closer to the physical things. Based on the reference architecture of IoT (ISO/IEC 30141), the RT-IoT conceptual model is established. The idea of edge subsystem is introduced. The sensing & con-trolling domain is the basis of the edge subsystem, and the edge subsystem usually must meet the hard real-time constraints. The model includes four perspectives, the time view, computation view, communication view, and control view. Each view looks, from a different angle, at how the time parameters impact an RT-IoT system.

关键词： Internet of Things(IoT) Real-time system Conceptual model View Hard/Soft real-time

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Big data analysis and data velocity

引用

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2015年第2期52卷 333-342页

作者： Chen, Shimin State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing100190 China

Big data poses three main challenges to the underlying data management systems: volume (a huge amount of data), velocity (high speed of data generation, data acquisition, and data updates), and variety (a large number of data types and data formats). In this paper, we focus on understanding the significance of velocity and discussing how to face the challenge of velocity in the context of big data analysis systems. We compare the requirements of velocity in transaction processing, data stream, and data analysis systems. Then we describe two of our recent research studies with an emphasis on the role of data velocity in big data analysis systems: 1) MaSM, supporting online data updates in data warehouse systems;2) LogKV, supporting high-throughput data ingestion and efficient time-window based joins in an event log processing system. Comparing the two studies, we find that storing incoming data updates is only the minimum requirement. We should consider velocity as an integral part of the data acquisition and analysis life cycle. It is important to analyze the characteristics of the desired big data analysis operations, and then to optimize data organization and data distribution schemes for incoming data updates so as to maintain or even improve the efficiency of big data analysis. ©, 2015, Science Press. All right reserved.

关键词： Data warehouses

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A Variable Batch Size Strategy for Large Scale Distributed DNN Training

A Variable Batch Size Strategy for Large Scale Distributed D...

引用

IEEE International Conference on Big Data and Cloud computing (BdCloud)

作者： Zhongzhe Hu Junmin Xiao Zhongbo Tian Xiaoyang Zhang Hongrui Zhu Chengji Yao Ninghui Sun Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences University of Chinese Academy of Sciences Western Institute of Advanced Technology Chinese Academy of Sciences Chongqing China Engine Megvii Technology Co.Ltd. Beijing China

ISBN: (数字)9781728143286

ISBN: (纸本)9781728143293

Large batch distributed synchronous stochastic gradient descent (SGD) has been widely used to train deep neural networks on a distributed memory system with multi-nodes, which can leverage parallel resources to reduce the number of iterative steps and speed up the convergence of training process. However, the large-batch SGD leads to a poor test accuracy, which would counteract the benefits of large scale parallel SGD. Existing solutions for large-batch training either significantly degrade accuracy or require massive additional hyper-parameter tuning. To overcome the difficulty above, we propose a novel variable batchsize strategy. With an in-depth analysis of the different stages in the recent multi-step schedule, we find that the training process at the first stage is sensitive to the batchsize, while different batchsize do not significantly impact the latter stages. Based on this discovery, we first claim that different stages of training should use different batchsize. Hence, the variable batchsize strategy is proposed for the large scale distributed training. Furthermore, in order to turn existing hyper-parameters automatically, an auto-tuning engine is designed for the variable batchsize strategy to achieve higher testing accuracy in the extremely large batchsize cases. By using our strategy, we successfully scale the batchsize to 120K in latter stages on ImageNet-1K with ResNet50 without accuracy loss and 128K with slight accuracy loss. The experimental evaluation on 2048 GPUs shows that the variable batchsize strategy with our auto-tuning engine could complete the training of ResNet-50 in 25 minutes. Furthermore, the new strategy successfully decreases the number of parameter updates by about 1.7 times compared with Facebook's multi-step schedule.

关键词： Training Schedules Neural networks Tuning Computational modeling Graphics processing units computer architecture

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