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TransGPerf:Exploiting Transfer Learning for Modeling Distributed Graph Computation Performance

Journal of computer Science & technology 2021年第4期36卷 778-791页

作者： Songjie Niu Shimin Chen State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China

It is challenging to model the performance of distributed graph *** formulation cannot easily capture the diversified factors and complex interactions in the *** learning methods require a large number of training samples to generate an accurate prediction ***,it is time-consuming to run the required graph computation tests to obtain the training *** this paper,we propose TransGPerf,a transfer learning based solution that can exploit prior knowledge from a source scenario and utilize a manageable amount of training data for modeling the performance of a target graph computation *** results show that our proposed method is capable of generating accurate models for a wide range of graph computation tasks on PowerGraph and *** outperforms transfer learning methods proposed for other applications in the literature.

关键词： performance modeling distributed graph computation deep learning transfer learning

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A Survey of Phase Change Memory systems

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Journal of computer Science & technology 2015年第1期30卷 121-144页

作者：夏飞蒋德钧熊劲孙凝晖 State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

As the scaling of applications increases, the demand of main memory capacity increases in order to serve large working set. It is difficult for DRAM （dynamic random access memory） based memory system to satisfy the memory capacity requirement due to its limited scalability and high energy consumption. Compared to DRAM, PCM （phase change memory） has better scalability, lower energy leakage, and non-volatility. PCM memory systems have become a hot topic of academic and industrial research. However, PCM technology has the following three drawbacks： long write latency, limited write endurance, and high write energy, which raises challenges to its adoption in practice. This paper surveys architectural research work to optimize PCM memory systems. First, this paper introduces the background of PCM. Then, it surveys research efforts on PCM memory systems in performance optimization, lifetime improving, and energy saving in detail, respectively. This paper also compares and summarizes these techniques from multiple dimensions. Finally, it concludes these optimization techniques and discusses possible research directions of PCM memory systems in future.

关键词： phase change memory memory system performance lifetime energy

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Parallel Incremental Frequent Itemset Mining for Large Data

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Journal of computer Science & technology 2017年第2期32卷 368-385页

作者： Yu-Geng Song Hui-Min Cui Xiao-Bing Feng State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

Frequent itemset mining （FIM） is a popular data mining issue adopted in many fields, such as commodity recommendation in the retail industry, log analysis in web searching, and query recommendation （or related search）. A large number of FIM algorithms have been proposed to obtain better performance, including parallelized algorithms for processing large data volumes. Besides, incremental FIM algorithms are also proposed to deal with incremental database updates. However, most of these incremental algorithms have low parallelism, causing low efficiency on huge databases. This paper presents two parallel incremental FIM algorithms called IncMiningPFP and IncBuildingPFP, implemented on the MapReduce framework. IncMiningPFP preserves the FP-tree mining results of the original pass, and utilizes them for incremental calculations. In particular, we propose a method to generate a partial FP-tree in the incremental pass, in order to avoid unnecessary mining work. Further, some of the incremental parallel tasks can be omitted when the inserted transactions include fewer items. IncbuildingPFP preserves the CanTrees built in the original pass, and then adds new transactions to them during the incremental passes. Our experimental results show that IncMiningPFP can achieve significant speedup over PFP （Parallel FPGrowth） and a sequential incremental algorithm （CanTree） in most cases of incremental input database, and in other cases IncBuildingPFP can achieve it.

关键词： incremental parallel FPGrowth data mining frequent itemset mining MapReduce

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Virtual resource monitoring in cloud computing

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Journal of Shanghai University(English Edition) 2011年第5期15卷 381-385页

作者：韩芳芳彭俊杰张武李青李建敦江钦龙袁勤 School of Computer Engineering and Science Shanghai University Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Science

Cloud computing is a new computing model. The resource monitoring tools are immature compared to traditional distributed computing and grid computing. In order to better monitor the virtual resource in cloud computing, a periodically and event-driven push （PEP） monitoring model is proposed. Taking advantage of the push and event-driven mechanism, the model can provide comparatively adequate information about usage and status of the resources. It can simplify the communication between Master and Work Nodes without missing the important issues happened during the push interval. Besides, we develop ＂mon＂ to make up for the deficiency of Libvirt in monitoring of virtual CPU and memory.

关键词： virtual resource monitoring cloud computing virtualization

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New methodologies for parallel architecture

New methodologies for parallel architecture

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作者： Fan, Dong-Rui Li, Xiao-Wei Li, Guo-Jie Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Moore's law continues to grant computer architects ever more transistors in the foreseeable future, and para-llelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are summarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc. © 2011 Springer Science+Business Media, LLC & Science Press, China.

关键词： Parallel architectures

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The design methodology of phoenix cluster system software stack

The design methodology of phoenix cluster system software st...

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2007 Asian technology Information Program's (ATIP's) 3rd Workshop on High Performance computing in China - Solution Approaches to Impediments for High Performance computing, CHINA HPC'07

作者： Zhan, Jianfeng Wang, Lei Tu, Bibo Wang, Hui Zhang, Zhihong Jin, Yi Wen, Yu Chen, Yuansheng Wang, Peng Qiu, Bizhu Meng, Dan Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781595939036

Though many research groups have explored the design methodology of cluster system software stack, few works discuss what constitutes a good one. In this paper, we choose four criteria throughout the lifecycle of cluster system software stack to evaluate its design methodology, including code reusability, evolveability, adaptability and manageability. According to the four criteria, we have proposed a management service-based layered design methodology and built a complete cluster system software stack for both scientific and business computing. Our practices and evaluations show our design methodology has advantages over others in terms of the proposed criteria. Copyright 2007 ACM.

关键词： Reusability

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Using index in the MapReduce framework

Using index in the MapReduce framework

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12th International Asia Pacific Web Conference, APWeb 2010

作者： An, Mingyuan Wang, Yang Wang, Weiping Key Laboratory of Computer System and Architecture Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China

ISBN: (纸本)9780769540122

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be nontrivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query. © 2010 IEEE.

关键词： MapReduce

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PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Journal of computer Science & technology 2009年第6期24卷 1086-1097页

作者：米伟冯晓兵贾耀仓陈莉薛京灵 Key Laboratory of Computer System and Architecture Institution of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.

关键词： DRAM row buffer page allocation locality optimization

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HTDet:A Clustering Method Using Information Entropy for Hardware Trojan Detection

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Tsinghua Science and technology 2021年第1期26卷 48-61页

作者： Renjie Lu Haihua Shen Zhihua Feng Huawei Li Wei Zhao Xiaowei Li the University of Chinese Academy of Sciences Beijing 101408China Beijing Institute of Computer Technology and Application Beijing 100854China the State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China

Hardware Trojans(HTs)have drawn increasing attention in both academia and industry because of their significant potential *** this paper,we propose HTDet,a novel HT detection method using information entropybased *** maintain high concealment,HTs are usually inserted in the regions with low controllability and low observability,which will result in that Trojan logics have extremely low transitions during the *** implies that the regions with the low transitions will provide much more abundant and more important information for HT *** HTDet applies information theory technology and a density-based clustering algorithm called Density-Based Spatial Clustering of Applications with Noise(DBSCAN)to detect all suspicious Trojan logics in the circuit under *** DBSCAN is an unsupervised learning algorithm,that can improve the applicability of *** addition,we develop a heuristic test pattern generation method using mutual information to increase the transitions of suspicious Trojan *** on circuit benchmarks demonstrate the effectiveness of HTDet.

关键词： Hardware Trojan(HT)detection information entropy Density-Based Spatial Clustering of Applications with Noise(DBSCAN) unsupervised learning clustering mutual information test patterns generation

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Memory Efficient Two-Pass 3D FFT Algorithm for Intel~ Xeon Phi^(TM) Coprocessor

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Journal of computer Science & technology 2014年第6期29卷 989-1002页

作者：刘益群李焱张云泉张先轶 Institute of Software Chinese Academy of Sciences University of Chinese Academy of Sciences Department of Computer Science and Technology Tsinghua University CCF ACM IEEE State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences

Equipped with 512-bit wide SIMD inst d large numbers of computing cores, the emerging x86-based Intel（R） Many Integrated Core （MIC） architecture ot only high floating-point performance, but also substantial off-chip memory bandwidth. The 3D FFT （three-di fast Fourier transform） is a widely-studied algorithm; however, the conventional algorithm needs to traverse the three times. In each pass, it computes multiple 1D FFTs along one of three dimensions, giving rise to plenty of rided memory accesses. In this paper, we propose a two-pass 3D FFT algorithm, which mainly aims to reduce of explicit data transfer between the memory and the on-chip cache. The main idea is to split one dimension into ensions, and then combine the transform along each sub-dimension with one of the rest dimensions respectively erence in amount of TLB misses resulting from decomposition along different dimensions is analyzed in detail. el parallelism is leveraged on the many-core system for a high degree of parallelism and better data reuse of loc On top of this, a number of optimization techniques, such as memory padding, loop transformation and vectoriz employed in our implementation to further enhance the performance. We evaluate the algorithm on the Intel（R） PhiTM coprocessor 7110P, and achieve a maximum performance of 136 Gflops with 240 threads in offload mode, which ts the vendor-specific Intel（R）MKL library by a factor of up to 2.22X.

关键词： 3D-FFT memory efficie many-core Many Integrated Core Intel(R) Xeon PhiTM

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