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检索条件"机构=Key Laboratory of Computer System and Architecture Institute of Computing Technology"
1009 条 记 录,以下是841-850 订阅
Extended selective encoding of scan slices for reducing test data and test power
Extended selective encoding of scan slices for reducing test...
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18th Asian Test Symposium, ATS 2009
作者: Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China
Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying sing... 详细信息
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An efficient methodology for power modeling and simulation of modern cell-based microprocessors
An efficient methodology for power modeling and simulation o...
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Midwest Symposium on Circuits and systems (MWSCAS)
作者: Ge Zhang Weiwu Hu Institute of Computing Technology Key Laboratory of Computer System and Architecture Beijing China
This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given ... 详细信息
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HPPNetSim: A parallel simulation of large-scale interconnection networks
HPPNetSim: A parallel simulation of large-scale interconnect...
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42nd Annual Simulation Symposium 2009, ANSS 2009, Part of the 2009 Spring Simulation Multiconference
作者: Cao, Zheng Xu, Jianwei Chen, Mingyu Zheng, Gui Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China
As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel int... 详细信息
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A case study of improving at-speed testing coverage of a gigahertz microprocessor
A case study of improving at-speed testing coverage of a gig...
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2009 16th IEEE International Conference on Electronics, Circuits and systems, ICECS 2009
作者: Qi, Zichu Liu, Hui Li, Xiangku Xu, Jun Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences PO Box 2704-25 Beijing 100190 China Beijing China Loongson Technologies Corporation Limited China
For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (Random Access Memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This pape... 详细信息
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HPPNetSim: A parallel simulation of large-scale interconnection networks
HPPNetSim: A parallel simulation of large-scale interconnect...
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2009 Spring Simulation Multiconference, SpringSim 2009
作者: Cao, Zheng Xu, Jianwei Chen, Mingyu Gui, Zheng Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China
As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel int... 详细信息
来源: 评论
A New Post-Silicon Debug Approach Based on Suspect Window
A New Post-Silicon Debug Approach Based on Suspect Window
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IEEE VLSI Test Symposium (VTS)
作者: Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences
Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observ... 详细信息
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Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors
Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...
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International Conference on computer and Information technology (CIT)
作者: Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), co... 详细信息
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Efficient binary translation system with low hardware cost
Efficient binary translation system with low hardware cost
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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)
作者: Weiwu Hu Qi Liu Jian Wang Songsong Cai Menghao Su Xiaoyu Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual ma... 详细信息
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Column-based RLE in row-oriented database
Column-based RLE in row-oriented database
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International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC
作者: Mingyuan An Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China
In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system perf... 详细信息
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Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP
Snooping and Ordering Ring - An Efficient Cache Coherence Pr...
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International Conference on Parallel and Distributed systems (ICPADS)
作者: Fei Cao Zhiyong Liu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China
Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. ... 详细信息
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