检索结果-内蒙古大学图书馆

Co-optimization of Dynamic/Static Test PoWer in Scan Test

电子学报(英文版) 2009年第1期18卷 54-58页

作者： WANG Wei HAN Yinhe LI Xiaowei FANG Fang School of Computer and Information Hefei University of Technology Hefei 230009 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China School of Management Hefei University of Technology Hefei 230009 China

Low-power design has become a challenge of test. We propose an effective low-power scan architecture named PowerSluice to minimize power consumption during scan test, which is based on scan chain modifications. On one hand, a kind of blocking logic is inserted into the scan chain to reduce the dynamic power and two kinds of controlling units are also inserted to decrease the leakage power during the shift cycle. On the other hand, using genetic algorithm, the exact values of control signals are found out to control the process. Experiments results indicate that this architecture can effectually reduce power during scan test with probably minimum area cost.

关键词：低功耗设计扫描测试静态测试动态优化合作控制单元电力消耗动态功耗

来源：评论

学校读者我要写书评

暂无评论

Empirical investigation of stochastic local search for maximum satisfiability

引用

Frontiers of computer Science 2019年第1期13卷 86-98页

作者： Yi CHU Chuan LUO Shaowei CAI Haihang YOU State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China State Key Laboratory of Mathematical Engineering and Advanced Computing Wuxi 214125China State Key Laboratory of Computer Science Institute of SoftwareChinese Academy of SciencesBeijing 100190China

The maximum satisfiability (MAX-SAT)problem is an important NP-hard problem in theory,and has a broad range of applications in *** local search (SLS)is becoming an increasingly popular method for solving ***,a powerful SLS algorithm called CCLS shows efficiency on solving random and crafted MAX-SAT ***,the performance of CCLS on solving industrial MAX-SAT instances lags far *** this paper,we focus on experimentally analyzing the performance of SLS algorithms for solving industrial MAXSAT ***,we conduct experiments to analyze why CCLS performs poor on industrial *** we propose a new strategy called additive BMS (Best from Multiple Selections)to ease the serious *** integrating CCLS and additive BMS,we develop a new SLS algorithm for MAXSAT called CCABMS,and related experiments indicate the efficiency of ***,we experimentally analyze the effectiveness of initialization methods on SLS algorithms for MAX-SAT,and combine an effective initialization method with CCABMS,resulting in an enhanced *** results show that our enhanced algorithm performs better than its state-of-the-art SLS competitors on a large number of industrial MAX-SAT instances.

关键词： empirical investigation stochastic local search maximum satisfiability industrial instances additive BMS

来源：评论

学校读者我要写书评

暂无评论

Labeled yon Neumann architecture for Software-Defined Cloud

引用

Journal of computer Science & technology 2017年第2期32卷 219-223页

作者： Yun-Gang Bao Sa Wang, Member, CCF State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China

As cloud computing is moving forward rapidly, cloud providers have been encountering great challenges： long tail latency, low utilization, and high interference. They intend to co-locate multiple workloads on a single server to improve the resource utilization. But the co-located applications suffer from severe performance interference and long tail latency, which lead to unpredictable user experience. To meet these challenges, software-defined cloud has been proposed to facilitate tighter coordination among application, operating system and hardware. Users＇ quality of service （QoS） requirements could be propagated all the way down to the hardware with differential management mechanisms. However, there is little hardware support to maintain and guarantee users＇ QoS requirements. To this end, this paper proposes Labeled von Neumann architecture （LvNA）, which introduces a labelling mechanism to convey more software＇s semantic information such as QoS and security to the underlying hardware. LvNA is able to correlate labels with various entities, e.g., virtual machine, process and thread, and propagate labels in the whole machine and program differentiated services based on rules. We consider LvNA to be a fundamental hardware support to the software-defined cloud.

关键词： software-defined cloud von Neumann architecture tail latency performance interference

来源：评论

学校读者我要写书评

暂无评论

High-performance genomic analysis framework with in-memory computing

引用

ACM SIGPLAN Notices 2018年第1期53卷 317-328页

作者： Li, Xueqi Tan, Guangming Wang, Bingchen Sun, Ninghui State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China University of Chinese Academy of Sciences China

ISBN: (纸本)9781450349116

In this paper, we propose an in-memory computing framework (called GPF) that provides a set of genomic formats, APIs and a fast genomic engine for large-scale genomic data processing. Our GPF comprises two main components: (1) scalable genomic data formats and API. (2) an advanced execution engine that supports efficient compression of genomic data and eliminates redundancies in the execution engine of our GPF. We further present both system and algorithm-specific implementations for users to build genomic analysis pipeline without any acquaintance of Spark parallel programming. To test the performance of GPF, we built a WGS pipeline on top of our GPF as a test case. Our experimental data indicate that GPF completes Whole-Genome-Sequencing (WGS) analysis of 146.9G bases Human Platinum Genome in running time of 24 minutes, with over 50% parallel efficiency when used on 2048 CPU cores. Together, our GPF framework provides a fast and general engine for large-scale genomic data processing which supports in-memory computing. © 2018 ACM.

关键词： Pipelines

来源：评论

学校读者我要写书评

暂无评论

Column-based RLE in row-oriented database

Column-based RLE in row-oriented database

引用

2009 International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC '09

作者： An, Mingyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424452187

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (Run-Length Encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage. © 2009 IEEE.

关键词： Query processing

来源：评论

学校读者我要写书评

暂无评论

A Robust and Power-Efficient SoC Implementation in 65 nm

引用

计算机科学技术学报（英文版） 2013年第4期28卷 682-688页

作者： Bin Xiao Yi-Fu Zhang Yan-Ping Gao Liang Yang Dong-Mei Wu Bao-Xia Fan State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100049 China Loongson Technology Corporation Limited Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

Godson2H is a complex SoC (system-on-Chip) of Godson series, which is a 117 mm2, 152 million transistors chip fabricated in 65 nm CMOS LP/GP process technology. It integrates a 1 GHz processor core and abundant high or low speed peripheral IO interfaces. To overcome on-chip-variation problems in deep submicron designs, many methods are adopted in clock tree, and PVT detectors are integrated for debug. To meet the low power constraints in different applications, most of state-of-the-art low power methods are used carefully, such as dynamic voltage and frequency scaling, power gating and aggressive multi-voltage design.

关键词： system-on-Chip on-chip-variation PVT detector low power hierarchical design flow

来源：评论

学校读者我要写书评

暂无评论

Intelligent test case generation based on branch and bound

引用

The Journal of China Universities of Posts and Telecommunications 2014年第2期21卷 91-97,103页

作者： XING Ying GONG Yun-zhan WANG Ya-wen ZHANG Xu-zhou State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications School of Electronic and Information Engineering Liaoning Technical University State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences

Path-oriented test case generation is in essence a constraint satisfaction problem （CSP） solved by search strategies, among which backtracking algorithms are widely used. In this article, the backtracking algorithm branch and bound （BB） is introduced to generate path-oriented test cases automatically. A model based on state space search is proposed to construct the search tree dynamically. The BB is optimized from two perspectives. Variable permutation with a heuristic rule to break ties is adopted for the branching operation, and interval computation with analysis on the monotony of branching conditions is utilized for the bounding operation. Empirical experiments show that the proposed method performs well with linear complexity, and reaches 100% coverage on some benchmark programs with an advantage over some static and dynamic algorithms.

关键词： test case generation constraint satisfaction problem branch and bound state space search

来源：评论

学校读者我要写书评

暂无评论

Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Wear rate leveling: Lifetime enhancement of PRAM with endura...

引用

作者： Dong, Jianbo Zhang, Lei Han, Yinhe Wang, Ying Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling © 2011 ACM.

关键词： Phase change memory

来源：评论

学校读者我要写书评

暂无评论

Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Flex memory: Exploiting and managing abundant off-chip optic...

引用

作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783981080179

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency. © 2011 EDAA.

关键词： Dynamic random access storage

来源：评论

学校读者我要写书评

暂无评论

SOOP: Efficient Distributed Graph Computation Supporting Second-Order Random Walks

引用

Journal of computer Science & technology 2021年第5期36卷 985-1001页

作者： Songjie Niu Dongyan Zhou State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of Sciences Beijing 100190China University of Chinese Academy of Sciences Beijing 100049China Bytedance Technology Beijing 100086China

The second-order random walk has recently been shown to effectively improve the accuracy in graph analysis *** work mainly focuses on centralized second-order random walk(SOW)*** algorithms rely on edge-to-edge transition probabilities to generate next random ***,it is prohibitively costly to store all the probabilities for large-scale graphs,and restricting the number of probabilities to consider can negatively impact the accuracy of graph analysis *** this paper,we propose and study an alternative approach,SOOP(second-order random walks with on-demand probability computation),that avoids the space overhead by computing the edge-to-edge transition probabilities on demand during the random ***,the same probabilities may be computed multiple times when the same edge appears multiple times in SOW,incurring extra cost for redundant computation and *** propose two optimization techniques that reduce the complexity of computing edge-to-edge transition probabilities to generate next random steps,and reduce the cost of communicating out-neighbors for the probability computation,*** experiments on real-world and synthetic graphs show that SOOP achieves orders of magnitude better performance than baseline precompute solutions,and it can efficiently computes SOW algorithms on billion-scale graphs.

关键词： second-order random walk(SOW) Node2Vec second-order PageRank distributed graph computation SOOP(second-order random walks with on-demand probability computation)

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：