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IEEE International Conference on computer Research and Development

作者： Li, Yu-Gang Zhao, Kun Huang, Yu-Qing Qiu, Zhen-Ge Liu, Zhi-Yong Beijing Lab. of Intelligent Information Technology School of Computer Science BIT Beijing 100081 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100081 China Institute of Computing Technology Chinese Academy Sciences Beijing China

ISBN: (纸本)9781612848372

Ray-tracing, can produce high-quality images, however, the use of ray-tracing has been limited due to its high demands on computational power and memory bandwidth, especially in the case of satellite imagery. In this paper, we propose a scalable parallel ray tracing algorithm of satellite imagery on a cluster of multi-core architecture. The algorithm combines demand-driven and data-driven models in order to reduce communication on the cost of maintaining redundant data. In order to make the most of computer's parallelism and increase computational efficiency, it combines two levels of parallelisms, the TLP parallelism brought by the many core architecture and the inter-node parallelism via MPI and OpenMP. Experiment results show that the algorithm is highly scalability. © 2011 IEEE.

关键词： Satellite imagery

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M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay

M-IVC: Using Multiple Input Vectors to Minimize Aging-Induce...

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Asian Test Symposium (ATS)

作者： Song Jin Yinhe Han Lei Zhang Huawei Li Xiaowei Li Guihai Yan Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architeture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors.

关键词： Niobium compounds Titanium compounds Degradation Stress Delay effects Circuits Threshold voltage Clocks Resists Aging

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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2007 IEEE International Test Conference, ITC

作者： Wang, Da Fan, Xiaoxin Fu, Xiang Liu, Hui Wen, Ke Li, Rui Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Beijing China Co. Ltd. Shanghai China

ISBN: (纸本)1424411289

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. Major DFT solutions are implemented which can meet high-volume manufacturing (HVM) and high quality test goals. © 2007 IEEE.

关键词： Design for testability

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GVE: Godson-T verification engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T verification engine for many-core architecture...

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2010 International Conference on Field-Programmable technology, FPT'10

作者： Lei, Zhengmeng Zhang, Lunkai Song, Fenglong Tang, Shibin Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424489817

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project. © 2010 IEEE.

关键词： Verification

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Fast path selection for testing of small delay defects considering path correlations

Fast path selection for testing of small delay defects consi...

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28th IEEE VLSI Test Symposium, VTS10

作者： He, Zijian Lv, Tao Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424466481

Statistical timing models have been proposed to describe delay variations in very deep sub-micro process technologies, which have increasingly significant influence on circuit performance. Under a statistical timing model, testing of a path can detect potential delay failures caused by different small delay defects. Due to path correlations, the potential delay failures captured by two different paths overlap between each other more or less. It is difficult to find a given number of paths that can capture most potential delay failures. In this paper, the path selection problem is converted to a minimal space intersection problem, and a greedy path selection heuristics is proposed, the key point of which is to calculate the probability that the paths in a specified path set all meet the delay constraint. Statistical timing analysis technologies and heuristics are used in the calculation. Experimental results show that the proposed approach is time-efficient and achieves a higher probability of capturing delay failures in comparison with conventional path selection approaches. ©2010 IEEE.

关键词： Defects

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A Dynamic Road Incident Information Delivery Strategy to Reduce Urban Traffic Congestion

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IEEE/CAA Journal of Automatica Sinica 2018年第5期5卷 934-945页

作者： Liang Qi Mengchu Zhou Wenjing Luan IEEE Department of Computer Scicnce and Technology Shandong University of Science and TechnologyQingdao 266590China Department of Computer Science Tongji UniversityShanghai 201804China Department of Electrical and Computer Engineering New Jersey Institute of TechnologyNewark NJ 07102USA Key Laboratory of Embedded System and Service Computing Ministry of EducationShanghai Electronic Transactions and Information Service Collaborative Innovation CenterDepartment of Com-puter ScienceTongji UniversityShanghai 201804China

Advanced information and communication technolo-gies can be used to facilitate traffic incident *** an incident is detected and blocks a road link,in order to reduce the incident-induced traffic congestion,a dynamic strategy to deliver incident information to selected drivers and help them make detours in urban areas is proposed by this ***-dependent shortest path algorithms are used to generate a subnetwork where vehicles should receive such information.A simulation approach based on an extended cell transmission model is used to describe traffic flow in urban networks where path information and traffic flow at downstream road links are well *** results reveal the influences of some major parameters of an incident-induced congestion dissipation process such as the ratio of route-changing vehicles to the total vehicles,operation time interval of the proposed strategy,traffic density in the traffic network,and the scope of the area where traffic incident information is *** results can be used to improve the state of the art in preventing urban road traffic congestion caused by incidents.

关键词： Cell transmission model(CTM) intelligent transportation systems(ITS) traffic incident management(TIM) urban traffic congestion

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Deterministic Circular Self Test Path

Deterministic Circular Self Test Path

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第十二届全国容错计算学术会议

作者： WEN Ke HU Yu LI Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100％ fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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Exploiting idle register classes for fast spill destination

Exploiting idle register classes for fast spill destination

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22nd ACM International Conference on Supercomputing, ICS'08

作者： Lu, Fang Wang, Lei Feng, Xiaobing Li, Zhiyuan Zhang, Zhaoqing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100191 China Department of Computer Sciences Purdue University West Lafayette IN 47906 United States

ISBN: (纸本)9781605581583

On today's microprocessors, there often exist several different types of registers, e.g. general purpose registers and floating point registers. A given program may use one type of registers much more frequently than other types. This creates an opportunity to employ the infrequently used registers as spill destinations for the more frequently used register types. In this paper, we present a code optimization method named idle register exploitation (IRE) to exploit such opportunities. We developed a model, called the IRE model, or IREM, to determine the static performance gains of IRE versus spilling to the stack. On a microprocessor with fast data paths between different types of registers, we find that IRE method speeds up the execution of the SPECint benchmark suite from 1.7% to 10%. In contrast, on microprocessors with less efficient data transfer paths, the performance gain is limited. In some cases, performance may even suffer degradation. This result argues strongly for the adoption of fast data paths between different types of registers for the purpose of reducing register spills, which is important in view of the increased significance of memory bottlenecks on future microprocessors. Copyright 2008 ACM.

关键词： Data transfer

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Data quantity governance for machine learning in materials science

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National Science Review 2023年第7期10卷 234-250页

作者： Yue Liu Zhengwei Yang Xinxin Zou Shuchang Ma Dahui Liu Maxim Avdeev Siqi Shi School of Computer Engineering and Science Shanghai University Shanghai Engineering Research Center of Intelligent Computing System Australian Nuclear Science and Technology Organisation School of Chemistry The University of Sydney State Key Laboratory of Advanced Special Steel School of Materials Science and Engineering Shanghai University Materials Genome Institute Shanghai University

Data-driven machine learning(ML) is widely employed in the analysis of materials structure-activity relationships,performance optimization and materials design due to its superior ability to reveal latent data patterns and make accurate ***,because of the laborious process of materials data acquisition,ML models encounter the issue of the mismatch between a high dimension of feature space and a small sample size(for traditional ML models) or the mismatch between model parameters and sample size(for deep-learning models),usually resulting in terrible ***,we review the efforts for tackling this issue via feature reduction,sample augmentation and specific ML approaches,and show that the balance between the number of samples and features or model parameters should attract great attention during data quantity *** this,we propose a synergistic data quantity governance flow with the incorporation of materials domain *** summarizing the approaches to incorporating materials domain knowledge into the process of ML,we provide examples of incorporating domain knowledge into governance schemes to demonstrate the advantages of the approach and *** work paves the way for obtaining the required high-quality data to accelerate materials design and discovery based on ML.

关键词： machine learning data governance data quantity materials science

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Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects

Test Generation for Crosstalk Glitches Considering Multiple ...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Minjin Zhang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade

As the feature size continues to scale into the nanometer era, crosstalk-induced effect begins to exert a more significant influence. In this paper, we address the condition of maximum crosstalk glitch noise considering multiple coupling effects and propose a novel test generation technique for this problem. A multiple crosstalk-induced glitch fault (MCGF) model is introduced, which gives information on one or more sub-paths to be sensitized to generate transitions coupled to a victim line. The test for an MCGF is a 2-vector pattern that sensitizes the transition signal along the sub-path to each aggressor line at the maximum aggressive time (MAT), and propagates the signal on a victim line to an output. A new structure, transition map (TM), is proposed to record all the possible arrival time of a line. The MAT of a victim line is calculated based on effective coupling capacitance (ECC). Therefore, the crosstalk-induced effects can be effectively identified, and exactly activated using the generated test patterns. Experiments on ISCAS89 benchmark circuit show that the proposed technique can be applied to circuits of reasonable sizes within acceptable time.

关键词： Crosstalk Circuit faults Timing Test pattern generators system testing Noise generators Coupling circuits Capacitance Circuit noise Automatic test pattern generation

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