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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"
517 条 记 录,以下是111-120 订阅
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A unified online fault detection scheme via checking of stability violation  09
A unified online fault detection scheme via checking of stab...
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2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
作者: Guihai, Yan Yinhe, Han Xiaowei, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100039 China
In ultra-deep submicro technology, two of the paramount reliability concerns are soft errors and device aging. Although intensive studies have been done to face the two challenges, most take them separately so far, th... 详细信息
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Testable critical path selection considering process variation
Testable critical path selection considering process variati...
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作者: Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China
Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testabi... 详细信息
来源: 评论
Green challenges to system software in data centers
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Frontiers of Materials Science 2011年 第3期5卷 353-368页
作者: Yuzhong SUN Yiqiang ZHAO Ying SONG Vajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China
With the increasing demand and the wide application of high performance commodity multi-core processors, both the quantity and scale of data centers grow dramatically and they bring heavy energy consumption. Researche... 详细信息
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A routing algorithm for random error tolerance in network-on-chip
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12th International Conference on Human-computer Interaction, HCI International 2007
作者: Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China Graduate University Chinese Academy of Sciences Beijing 100080 China
In DSM and nanometer technology, there will present more and more new fault types, which are difficult to predict and avoid. Applying fault tolerant algorithms to achieve reliable on-chip communication is one of the m... 详细信息
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Protein structure superposition by curve moment invariants and iterative closest point
Protein structure superposition by curve moment invariants a...
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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE
作者: Xu, Dong Li, Hua Gu, Tongjun Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Center for Systems Biology Institute of Biophysics Chinese Academy of Sciences Graduate University Chinese Academy of Sciences
Superimpose one protein tertiary structure to another can help to find similarity between them and further identify functional and evolutionary relationships. We first extract invariant features under rigid body trans... 详细信息
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Fetching primary and redundant instructions in turn for a fault-tolerant embedded microprocessor
Fetching primary and redundant instructions in turn for a fa...
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14th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2008
作者: Zhang, Shijian Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate School of the Chinese Academy of Sciences Beijing 100039 China
With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fau... 详细信息
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Extended selective encoding of scan slices for reducing test data and test power
Extended selective encoding of scan slices for reducing test...
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18th Asian Test Symposium, ATS 2009
作者: Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China
Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying sing... 详细信息
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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture  11
Poster: Revisiting virtual channel memory for performance an...
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Proceedings of the international conference on Supercomputing
作者: Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States
In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous r... 详细信息
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Eliminating data invalidation in debugging multiple-clock chips
Eliminating data invalidation in debugging multiple-clock ch...
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作者: Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China
A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data... 详细信息
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A remote debugging system for OpenMP parallel program
A remote debugging system for OpenMP parallel program
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2011 International Conference on Transportation, Mechanical, and Electrical Engineering, TMEE 2011
作者: Chai, Hua Shi, Qinqin Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China Department of Computer Science and Information Engineering Shanghai Institute of Technology Shanghai 201418 China
A remote debugging system for OpenMP parallel program is presented in this paper. The system consists of two parts, namely, an integrated debugging environment running on the clent-side and a background daemon running... 详细信息
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