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2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09

作者： Guihai, Yan Yinhe, Han Xiaowei, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783981080155

In ultra-deep submicro technology, two of the paramount reliability concerns are soft errors and device aging. Although intensive studies have been done to face the two challenges, most take them separately so far, thereby failing to reach better performance-cost tradeoffs. To support a more efficient design tradeoff, we present a new fault model, Stability Violation, derived from analysis of signal behavior. Furthermore, we propose a unified fault detection scheme - Stability Violation based Fault Detection (SVFD), by which the soft errors (both Single Event Upset and Single Event Transient), aging delay, and delay faults can be uniformly handled. SVFD can greatly facilitate soft error-resistant and aging-aware designs. SVFD is validated by conducting a set of intensive Hspice simulations targeting 65nm CMOS technology. Experimental results show that SVFD has more robust capability for fault detection than previous schemes at comparable overhead in terms of area, power, and performance. © 2009 EDAA.

关键词： Fault detection

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Testable critical path selection considering process variation

Testable critical path selection considering process variati...

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作者： Fu, Xiang Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academic of Science Beijing 100190 China Graduate University of Chinese Academic of Sciences Beijing 100039 China

Critical path selection is very important in delay testing. Critical paths found by conventional static timing analysis (STA) tools are inadequate to represent the real timing of the circuit, since neither the testability of paths nor the statistical variation of cell delays caused by process variation is considered. This paper proposed a novel path selection method considering process variation. The circuit is firstly simplified by eliminating non-critical edges under statistical timing model, and then divided into sub-circuits, while each sub-circuit has only one prime input (PI) and one prime output (PO). Critical paths are selected only in critical sub-circuits. The concept of partially critical edges (PCEs) and completely critical edges (CCEs) are introduced to speed up the path selection procedure. Two path selection strategies are also presented to search for a testable critical path set to cover all the critical edges. The experimental results showed that the proposed circuit division approach is efficient in path number reduction, and PCEs and CCEs play an important role as a guideline during path selection. Copyright © 2010 The institute of Electronics.

关键词： Delay circuits

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Green challenges to system software in data centers

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Frontiers of Materials Science 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Vajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors, both the quantity and scale of data centers grow dramatically and they bring heavy energy consumption. Researchers and engineers have applied much effort to reducing hardware energy consumption, but software is the true consumer of power and another key in making better use of energy. system software is critical to better energy utilization, because it is not only the manager of hardware but also the bridge and platform between applications and hardware. In this paper, we summarize some trends that can affect the efficiency of data centers. Meanwhile, we investigate the causes of software inefficiency. Based on these studies, major technical challenges and corresponding possible solutions to attain green system software in programmability, scalability, efficiency and software architecture are discussed. Finally, some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center,power efficient system software

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A routing algorithm for random error tolerance in network-on-chip

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12th International Conference on Human-computer Interaction, HCI International 2007

作者： Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences 100080 Beijing China Graduate University Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9783540731092

In DSM and nanometer technology, there will present more and more new fault types, which are difficult to predict and avoid. Applying fault tolerant algorithms to achieve reliable on-chip communication is one of the most important issues of Network-on-Chip (NoC). This paper reviews the main on-chip fault tolerant communication algorithms and then proposes a new routing algorithm with end-to-end feedback. The average transmission latency, power consumption and reliability are compared with other techniques. As experiments show, the proposed algorithm has lower latency, lower power consumption compared with those of others, and it can provide high reliability. © Springer-Verlag Berlin Heidelberg 2007.

关键词： Routing algorithms

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Protein structure superposition by curve moment invariants and iterative closest point

Protein structure superposition by curve moment invariants a...

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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Xu, Dong Li, Hua Gu, Tongjun Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Center for Systems Biology Institute of Biophysics Chinese Academy of Sciences Graduate University Chinese Academy of Sciences

ISBN: (纸本)1424411203

Superimpose one protein tertiary structure to another can help to find similarity between them and further identify functional and evolutionary relationships. We first extract invariant features under rigid body transformation for each protein backbone which is represented by alpha-carbons of all the residues. Then, the invariant features are embedded with Iterative Closest Point algorithm for superposition. With several initialized orientations, pairwise alignment can be achieved accurately only by few iterations. Experiments indicate that our proposed algorithm is competitive with several well-known algorithms and with smallest root mean squared distance. © 2007 IEEE.

关键词： Proteins

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Fetching primary and redundant instructions in turn for a fault-tolerant embedded microprocessor

Fetching primary and redundant instructions in turn for a fa...

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14th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2008

作者： Zhang, Shijian Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate School of the Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9780769534480

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor's instruction fetch bandwidth on a program's performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor. © 2008 IEEE.

关键词： Fault detection

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Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

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18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

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Poster: Revisiting virtual channel memory for performance and fairness on multi-core architecture 11

Poster: Revisiting virtual channel memory for performance an...

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Proceedings of the international conference on Supercomputing

作者： Chen, Licheng Huang, Yongbing Bao, Yungang Mutlu, Onur Tan, Guangming Chen, Mingyu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Graduate School of Chinese Academy of Sciences China Carnegie Mellon University United States

ISBN: (纸本)9781450301022

In modern multi-core chip architecture, the DRAM system is shared by more and more cores and high bandwidth I/O devices. This trend would make the problem of request contention and un-fairness more serious. Previous research focused on memory sche-duling mechanisms to efficiently and fairly serve memory requests generated by multiple cores. However, the performance is mod-erately improved due to the limited bank-level parallelism in preva-lent DRAM chips. Based on the observation that virtual channel memory (VCM) provides more opportunities for exploiting MLP because it has more channel buffers than banks in conventional DRAM chip, we evaluate VCM technology as an alternative to DRAM for addressing the issues of contention, unfairness and MLP. In this work we implement VCM and leverage the state of art scheduling mechanism on a multi-core architecture. The experi-mental results show that (i) VCM with 32 channels improves ho-mogeneous workloads' IPC by 2.08X on a 16-core system compared to the system with conventional DRAM chips, causing extra area cost by 0.5%, and dynamic and background power pe-nalties by only 5.8% and 0.03% respectively. (ii) For heterogene-ous workloads, VCM significantly reduces unfairness by 82.0% as well as improves the workloads' performance by 1.86X in term of system throughput. © 2011 Authors.

关键词： Dynamic random access storage

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Eliminating data invalidation in debugging multiple-clock chips

Eliminating data invalidation in debugging multiple-clock ch...

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作者： Gao, Jianliang Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China School of Information Science and Engineering Central South University China

ISBN: (纸本)9783981080179

A critical concern for post-silicon debug is the need to control the chip at clock cycle level. In a single clock chip, run-stop control can be implemented by gating the clock signal using a stop signal. However, data invalidation might occur when it comes to multiple-clock chips. In this paper, we analyze the possible data invalidation, including data repetition and data loss, when stopping and resuming a multiple-clock chip. Furthermore, we propose an efficient solution to eliminate data repetition and data loss. Theoretical analysis and simulation experiments are both conducted for the proposed solution. We implement the proposed Design-for-Debug (DfD) circuit with SMIC 0.18/Ltm technology and simulate the data transfer across clock domains using SPICE tool. The results show that both data repetition and data loss can be avoided with the proposed solution, even if metastability occurs. © 2011 EDAA.

关键词： Clocks

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A remote debugging system for OpenMP parallel program

A remote debugging system for OpenMP parallel program

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2011 International Conference on Transportation, Mechanical, and Electrical Engineering, TMEE 2011

作者： Chai, Hua Shi, Qinqin Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China Department of Computer Science and Information Engineering Shanghai Institute of Technology Shanghai 201418 China

ISBN: (纸本)9781457717017

A remote debugging system for OpenMP parallel program is presented in this paper. The system consists of two parts, namely, an integrated debugging environment running on the clent-side and a background daemon running on the server-side. Information exchange between the two sides is accomplished through the socket-based network communication technology. The remote debugging function is realized by the automatic instrumentation technology at code level based on syntax tree. Instance tests show that the system can provide remote users with correctness checking, performance analysis and other debugging functions for OpenMP parallel programs. The user interface is simple and very easy to use. © 2011 IEEE.

关键词： User interfaces

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