As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placem...
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With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-fo...
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Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizin...
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This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanomet...
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This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processorsIn this paper, we use the modular design methodology and scaleable design-for-testability(DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further moreThe experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.
Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observ...
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ISBN:
(纸本)9781424437696
Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.
IEEE 802.15.4/ZigBee sensor networks support small power consumption and node expansion compared to other network standards for WSN. Body sensor networks (BSN) require a number of sensors for sensing medical informati...
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The information technology has been recognized as one of the most important means to improve health care and curb its ever-increasing cost. However, existing efforts mainly focus on informatization of hospitals or med...
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The world faces an energy problem. Oil supply is gradually running out. Its use is polluting the planet with greenhouse gas. Most alternative energy sources also pose some environmental problems. Hence the efficient u...
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As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study...
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Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP sys...
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