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Cross-layer optimized placement and routing for FPGA soft error mitigation

Cross-layer optimized placement and routing for FPGA soft er...

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作者： Huang, Keheng Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that the statistical variation of the application level factor is significant. Hence in this work, we first propose a cube-based analysis to efficiently and accurately evaluate the application level factor. And then we propose a cross-layer optimized placement and routing algorithm to reduce the SER by incorporating the application level and the physical level factor together. Experimental results show that, the average difference of the application level factor between our cube-based method and Monte Carlo golden simulation is less than 0.01. Moreover, compared with the baseline VPR placement and routing technique, the cross-layer optimized placement and routing algorithm can reduce the SER by 14% with no area and performance overhead. © 2011 EDAA.

关键词： Field programmable gate arrays (FPGA)

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On diagnosis of multiple faults using compacted responses

On diagnosis of multiple faults using compacted responses

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作者： Ye, Jing Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

With the exponential growth in the number of transistors, not only test data volume and test application time may increase, but also multiple faults may exist in one chip. Test compaction has been a de-facto design-for-testability technique to reduce the test cost. However, the compacted test responses make multiple-fault diagnosis rather difficult. When there is no space compactor, the most likely suspect fault is considered producing the failing responses most similar to the failing responses observed from the automatic test equipment. But when compactor exists, those suspect faults may no longer have the same high possibility of being the actual faults. To address this problem, we introduce a novel metric explanation necessity. By using both of the new metric and the traditional metric explanation capability, we evaluate the possibility of a suspect fault to be the actual fault. For ISCAS'89 and ITC'99 benchmark circuits equipped with extreme space compactors, experimental results show that 98.8% of the top-ranked suspect faults hit the actual faults, outperforming a previous work by 11.3%. © 2011 EDAA.

关键词： Design for testability

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A cost-effective substantial-impact-filter based method to tolerate voltage emergencies

A cost-effective substantial-impact-filter based method to t...

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作者： Pan, Songjun Hu, Yu Hu, Xing Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

ISBN: (纸本)9783981080179

Supply voltage fluctuation caused by inductive noises has become a critical problem in microprocessor design. A voltage emergency occurs when supply voltage variation exceeds the acceptable voltage margin, jeopardizing the microprocessor reliability. Existing techniques assume all voltage emergencies would definitely lead to incorrect program execution and prudently activate rollbacks or flushes to recover, and consequently incur high performance overhead. We observe that not all voltage emergencies result in external visible errors, which can be exploited to avoid unnecessary protection. In this paper, we propose a substantial-impact-filter based method to tolerate voltage emergencies, including three key techniques: 1) Analyze the architecture-level masking of voltage emergencies during program execution;2) Propose a metric intermittent vulnerability factor for intermittent timing faults (IV F itf) to quantitatively estimate the vulnerability of microprocessor structures (load/store queue and register file) to voltage emergencies;3) Propose a substantial-impact-filter based method to handle voltage emergencies. Experimental results demonstrate our approach gains back nearly 57% of the performance loss compared with the once-occur-then-rollback approach. © 2011 EDAA.

关键词： Cost effectiveness

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A Case Study: Low Power Design-for-Testability Features of a Multi-core Processor Godson-T

A Case Study: Low Power Design-for-Testability Features of a...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Da Wang Dongrui Fan Yu Hu Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

This paper describes the low power test challenges and features of a multi-core processor, Godson-T, which contains 16 identical coresSince the silicon design technology scales to ultra deep submicron and even nanometers, the complexity and cost of testing is growing up, and the test power of such designs is extremely curious, especially for multicore processorsIn this paper, we use the modular design methodology and scaleable design-for-testability(DFT) structure to achieve low test power, at the same time, an improved test pattern generation method is studied to reduce test power further moreThe experimental results from the real chip show that the test power and test time are well balanced while achieving acceptable test coverage and cost.

关键词： design-for-testability(DFT),multi-core processor,very large scale integration(VLSI),power reduction,pattern filling,multi-capture

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A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

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IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

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Design issues in ZigBee-based sensor network for healthcare applications

Design issues in ZigBee-based sensor network for healthcare ...

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2012 9th IEEE International Conference on Networking, Sensing and Control, ICNSC 2012

作者： Choi, Jin Soo Zhou, MengChu Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China

ISBN: (纸本)9781467303880

IEEE 802.15.4/ZigBee sensor networks support small power consumption and node expansion compared to other network standards for WSN. Body sensor networks (BSN) require a number of sensors for sensing medical information from human body, and low power consumption to monitor a patient's status for a long time. However, ZigBee has limited bandwidth and is thus hard to support real time data transmission because of the adoption of CSMA-CA as its medium access control (MAC) protocol. In this paper, we will analyze the reasonable number of nodes, size of payload and packet interval for best QoS for such network. It is found that an appropriate MAC parameters setting can improve the QoS compared to the default setting in IEEE 802.15.4 specification. The effective data rate, average end-to-end delay and packet delivery ratio are found via simulation for various network settings. The results are useful for the construction of ZigBee networks for patient monitoring and care. © 2012 IEEE.

关键词： Medium access control

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Web service composition techniques in a health care service platform

Web service composition techniques in a health care service ...

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2011 IEEE 9th International Conference on Web Services, ICWS 2011

作者： Wang, Pengwei Ding, Zhijun Jiang, Changjun Zhou, Mengchu Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States

ISBN: (纸本)9780769544632

The information technology has been recognized as one of the most important means to improve health care and curb its ever-increasing cost. However, existing efforts mainly focus on informatization of hospitals or medical institutions within organizations, and few are directly oriented to individuals. The strong demand for various health services from customers calls for the creation of powerful individual-oriented personalized health care service systems. Web service composition (WSC) and related technologies can greatly help one build such systems. This paper aims to present a newly developed platform called a Public-oriented Health care Information Service Platform (PHISP) and several novel WSC techniques that are used to build it. Among them include WSC techniques that can well support branch and parallel structures. © 2011 IEEE.

关键词： Web services

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Model predictive control for HVAC systems - A review

Model predictive control for HVAC systems - A review

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2013 IEEE International Conference on Automation Science and Engineering, CASE 2013

作者： Kwadzogah, Roger Zhou, Mengchu Li, Sisi Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07013 United States Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 201804 China

ISBN: (纸本)9781479915156

The world faces an energy problem. Oil supply is gradually running out. Its use is polluting the planet with greenhouse gas. Most alternative energy sources also pose some environmental problems. Hence the efficient use of energy must be an integral part of any solution to them. Whenever possible, one must use advanced control engines and technologies to achieve the highest energy efficiency. In Heating Ventilation and Air Conditioning (HVAC) industry, much research has identified a number of energy-saving control methods. Derived from optimal control theory, Model Predictive Control (MPC) is one of them. This paper presents a comprehensive review of its applications to HVAC systems. © 2013 IEEE.

关键词： Model predictive control

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Virtualizing modern high-speed interconnection networks with performance and scalability

Virtualizing modern high-speed interconnection networks with...

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作者： Li, Bo Huo, Zhigang Zhang, Panyong Meng, Dan National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542201

As one of the most important enabling technologies of cloud computing, virtualization brings to HPC good manageability, online system maintenance, performance isolation and fault isolation. Furthermore, previous study on VMM-bypass I/O that virtualizes OS-bypass networks (e.g. Infini- Band) relieved the worry of performance degradation coming along with virtualization. In this paper, we address the scalability challenges imposed upon OS-bypass networks under virtualized environments. The eXtended Reliable Connection (XRC) transport, proposed in modern high-speed interconnection networks to address the scalability problem in large scale applications, would not work in virtualized environments. To solve the problem, we propose VM-proof XRC design to eliminate the scalability gap between virtualized and native environments. Prototype evaluation shows that the virtualization of modern high-speed interconnection networks could get the same raw performance and scalability as in native non-virtualized environment with our VM-proof XRC design. The connection memory scalability shows a potential of 16 times improvement on virtualized clusters composed of 16-core nodes. © 2010 IEEE.

关键词： Scalability

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Processes scheduling on heterogeneous multi-core architecture with hardware support

Processes scheduling on heterogeneous multi-core architectur...

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IEEE International Conference on Networking, Architecture and Storage

作者： Hao, Shouqing Liu, Qi Zhang, Longbing Wang, Jian Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769545097

Heterogeneous Chip Multi-Processors (heter-CMP) provide suitable resources to various applications and could get more benefits on performance than homogeneous CMP. To fully develop the performance of the heter-CMP system, the applications should be scheduled to the proper cores by the scheduler of the operating system according to their behaviours. Besides, the last level cache (LLC) miss rate is often used as the metric to identify the application features. However, the LLC miss rate could not reflect the application behaviours accurately since the memory access delay, the most important application character is related to patterns of the memory access and many other issues. To improve the accuracy of scheduling on the heter-CMP system, this paper supplies performance counters for the LLC miss penalty to monitor application behaviours. Based on that, the latency-aware scheduling algorithm for asymmetry chip multi-processors (LA-ACMP) is proposed and implemented. Those hardware supports are implemented on the Godson-3 multi-core RTL and simulator and the LA-ACMP algorithm is integrated to the Linux kernel. The performance evaluation on those platforms shows that the LA-ACMP algorithm with LLC miss penalty outperforms the algorithm with LLC miss rate about 32.4%, and outperforms the original schedule algorithm about 18.4%. © 2011 IEEE.

关键词： Scheduling algorithms

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