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BTMD: A framework of binary translation based malcode detector

BTMD: A framework of binary translation based malcode detect...

引用

4th International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC 2012

作者： Shan, Zheng Guo, Haoran Pang, Jianmin Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China National Digital Switching System Engineering and Technology Research Center Zhengzhou China

ISBN: (纸本)9780769548104

Binary Translation technology is used to convert binary code of one Instruction Set Architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate. © 2012 IEEE.

关键词： Binary codes

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Extendable pattern-oriented optimization directives

Extendable pattern-oriented optimization directives

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作者： Cui, Huimin Xue, Jingling Wang, Lei Yang, Yang Feng, Xiaobing Fan, Dongrui Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Beijing China School of Computer Science and Engineering University of New South Wales Sydney NSW Australia

Algorithm-specific, that is, semantic-specific optimizations have been observed to bring significant performance gains, especially for a diverse set of multi/many-core architectures. However, current programming models and compiler technologies for the state-of-the-art architectures do not exploit well these performance opportunities. In this article, we propose a pattern-making methodology that enables algorithm-specific optimizations to be encapsulated into "optimization patterns". Such optimization patterns are expressed in terms of preprocessor directives so that simple annotations can result in significant performance improvements. To validate this new methodology, a framework, named EPOD, is developed to map these directives into the underlying optimization schemes for a particular architecture. It is difficult to create an exact performance model to determine an optimal or near-optimal optimization scheme (including which optimizations to apply and in which order) for a specific application, due to the complexity of applications and architectures. However, it is trackable to build individual optimization components and let compiler developers synthesize an optimization scheme from these components. Therefore, our EPOD framework provides an Optimization Programming Interface (OPI) for compiler developers to define new optimization schemes. Thus, new patterns can be integrated into EPOD in a flexible manner. We have identified and implemented a number of optimization patterns for three representative computer platforms. Our experimental results show that a pattern-guided compiler can outperform the state-of-theart compilers and even achieve performance as competitive as hand-tuned code. Therefore, such a patternmaking methodology represents an encouraging direction for domain experts' experience and knowledge to be integrated into general-purpose compilers. © 2012 ACM.

关键词： Semantics

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A testability-aware low power architecture

A testability-aware low power architecture

引用

25th IEEE International system-on-Chip Conference, SOCC 2012

作者： Wang, Gang Wang, Jian Qi, Zi-Chu Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Loongson Technology Corporation Limited Beijing 100190 China

ISBN: (纸本)9781467312950

Test power consumption is becoming a major concern in low power integrated circuits(ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption. © 2012 IEEE.

关键词： Electric power utilization

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Cache locking for network processing acceleration

Cache locking for network processing acceleration

引用

2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012

作者： Su, Wen Gao, Xiang Wang, Jing You, Ruibang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China Institute of Computing Technology Chinese Academy of Sciences China Graduate University Chinese Academy of Sciences China Loongson Technology Corporation Limited China

ISBN: (纸本)9780769547015

With the dramatic increase in network speed during the past ten years, network processing efficiency has been significantly decreased. In this paper, we propose a network accelerating scheme, which employs cache locking method to reduce data and instruction accessing latency. Interrupts handling and buffer maintenance overheads are obviously decreased. Experimental results show that our solution increases about 22% network bandwidth and reduces 10% latency. © 2012 IEEE.

关键词： Locks (fasteners)

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Design issues in ZigBee-based sensor network for healthcare applications

Design issues in ZigBee-based sensor network for healthcare ...

引用

2012 9th IEEE International Conference on Networking, Sensing and Control, ICNSC 2012

作者： Choi, Jin Soo Zhou, MengChu Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China

ISBN: (纸本)9781467303880

IEEE 802.15.4/ZigBee sensor networks support small power consumption and node expansion compared to other network standards for WSN. Body sensor networks (BSN) require a number of sensors for sensing medical information from human body, and low power consumption to monitor a patient's status for a long time. However, ZigBee has limited bandwidth and is thus hard to support real time data transmission because of the adoption of CSMA-CA as its medium access control (MAC) protocol. In this paper, we will analyze the reasonable number of nodes, size of payload and packet interval for best QoS for such network. It is found that an appropriate MAC parameters setting can improve the QoS compared to the default setting in IEEE 802.15.4 specification. The effective data rate, average end-to-end delay and packet delivery ratio are found via simulation for various network settings. The results are useful for the construction of ZigBee networks for patient monitoring and care. © 2012 IEEE.

关键词： Medium access control

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A novel HW/SW partitioning with SIMD instructions for AVS video decoder

A novel HW/SW partitioning with SIMD instructions for AVS vi...

引用

2012 IEEE 7th International Conference on Networking, Architecture and Storage, NAS 2012

作者： Chen, Liwei Cong, Ming Huang, Jing Li, Ling Liu, Hongwei Qian, Cheng Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769547220

In this paper, we propose a novel HW/SW partitioning with SIMD instructions for the real-time AVS video decoder. As the SIMD instructions instead of hardware are used to optimize video decoding, our approach achieves an optimal balance between performance and programmability. We implement the proposed HW/SW partitioning on a 32-bit RISC processor with 256-bit vector extension, and evaluate the performance using some standard high-quality streams of AVS. Results show that the video decoding system can support the real-time decoding of AVS HD video streams. © 2012 IEEE.

关键词： Decoding

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A testability-aware low power architecture

A testability-aware low power architecture

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IEEE International SOC Conference

作者： Gang Wang Jian Wang Zi-Chu Qi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Test power consumption is becoming a major concern in low power integrated circuits (ICs). This paper presents a revised low power compression architecture for scan test. In this paper, the variance in power consumption is used to select test pattern during scan test, and a low power feedback MUX is added to the scan chains. Simulation results by mathematical methods show that the proposed test architecture is promising in reduction of power consumption.

关键词： Power demand computer architecture Switches Clocks Vectors Switching circuits Compaction

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MCC: A Load Balancing and Deadlock Free Interconnect Network for Cache Coherent Chip Multiprocessors

MCC: A Load Balancing and Deadlock Free Interconnect Network...

引用

IEEE International Conference on Computational Science and Engineering, CSE

作者： Liwei Chen Guangfei Zhang Huandong Wang Wenxiang Wang Ling Li Hua Jing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

As the number of cores in chip multiprocessors (CMPs) increases, network-on-chip (NoC) has become a major role in ensuring performance and power scalability. In this paper, we propose multiple-combinational-channel (MCC), a load balancing and deadlock free interconnect network for cache-coherent non-uniform memory accessing (CC-NUMA). In order to make load more balancing and reduce power dissipation, we combine low usage channels and make high usage channels independent and wide enough, since messages transmitted over NoC have different widths and injection rates. Furthermore, based on the in-depth analysis of network traffic, we summarize four traffic patterns and establish several rules to avoid protocol-level deadlock. We implement MCC on a 16-core CMPs, and evaluate the power and performance using universal workloads. The experimental results show that MCC reduces nearly 21% power than multiple-physical-channel with similar throughput. Moreover, MCC improves 10% performance with similar area and power, compared to packet-switching architecture with virtual channels.

关键词： system recovery system-on-a-chip Program processors Bandwidth Load management Throughput Scalability

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Battery discharge characteristics of wireless sensors in building applications

Battery discharge characteristics of wireless sensors in bui...

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2012 9th IEEE International Conference on Networking, Sensing and Control, ICNSC 2012

作者： Guo, Wenqi Healy, William M. Zhou, MengChu Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark NJ 07102 United States National Institute of Standards and Technology Gaithersburg MD 20899 United States Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai 200092 China

ISBN: (纸本)9781467303880

Sensor nodes in wireless networks often use batteries as their source of energy, but replacing or recharging exhausted batteries in a deployed network can be difficult and costly. Therefore, prolonging battery life becomes a principal objective in the design of wireless sensor networks (WSNs). There is little published data that quantitatively analyze a sensor node's lifetime under different operating conditions. This paper presents several experiments to quantify the impact of key wireless sensor network design and environmental parameters on battery performance. Our testbed consists of MicaZ motes, commercial alkaline batteries, and a suite of techniques for measuring battery performance. We evaluate known parameters, such as communication distance, working channel and operating power that play key roles in battery performance. Through extensive real battery discharge measurements, we expect our results to serve as a quantitative basis for future research in designing and implementing battery-efficient sensing applications and protocols. © 2012 IEEE.

关键词： Zigbee

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Adaptive rate-distortion prediction for multiple reference selection and inter-mode decision

Adaptive rate-distortion prediction for multiple reference s...

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13th Pacific-Rim Conference on Multimedia, PCM 2012

作者： Zhao, Tiesong Zhang, Yun Kwong, Sam Wang, Hanli Chen, Qian Shenzhen Institute of Advanced Technology Chinese Academy of Sciences Shenzhen China Department of Computer Science City University of Hong Kong Hong Kong Hong Kong Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai China

ISBN: (纸本)9783642347771

To minimize Rate-Distortion (RD) cost in video coding, RD Optimization (RDO) technique is adopted, which also brings increasingly computational complexity in Motion Estimation (ME), multiple reference selection and mode decision. In this paper, a Gaussian model based adaptive RD cost prediction method is developed to jointly speed up multiple reference selection and inter-mode decision. Besides the ability of achieving good coding efficiency with much reduced computational power, our method is also with two major advantages. First, it can achieve robust performance, including computational complexity reduction and almost intact video quality, with a wide range of video sequences resolutions and even for various scene changes;second, it could be either individually used or combined with the other efficient mode decision algorithms, and in both cases, our method could achieve remarkable performance, which is revealed by exhaustive experimental results. © 2012 Springer-Verlag.

关键词： Image coding

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