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An architecture description language based on dynamic description logics for self-healing systems

International Journal of Advancements in computing technology 2012年第18期4卷 89-96页

作者： Wang, Zhuxiao Peng, Hui Guo, Jing Wu, Kehe Cui, Wenchao Wang, Xiaofeng School of Control and Computer Engineering State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources North China Electric Power University Beijing 102206 China Education Technology Center Beijing International Studies University Beijing 100024 China National Computer Network Emergency Response Technical Team/Coordination Center of China Beijing 100029 China School of Control and Computer Engineering Institute of Electric Information Security Engineering Research Center of Power Information North China Electric Power University Beijing 102206 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

As biological systems exhibit adaptation, healing and robustness in the face of changing environmental behavior, this paradigm has actuated research dealing with the concept of self-healing systems, which attempt to heal themselves in the sense of recovering from malicious attacks and rectifying of system faults. The goal of self-healing systems is to provide survivable systems that require high dependability, robustness, adaptability, and availability. Such systems maintain one or more models, whether external or internal, at run time as a basis for identifying problems and resolving them. This article describes an architectural description language, called ADML, which is being developed as a new formal language and/or conceptual model for representing evolving software architectures. The ADML embraces dynamic change as a fundamental consideration, supports a broad class of adaptive changes at the architectural level, and offers a uniform way to represent and reason about both static and dynamic aspects of self-healing systems. Because the ADML is based on the Dynamic Description Logic DDL(SHON (D)), which can represent both dynamic semantics and static semantics under a unified logical framework, architectural ontology entailment for the ADML languages can be reduced to knowledge base satisfiability in DDL(SHON (D)), and dynamic description logic algorithms and implementations can be used to provide reasoning services for ADML. In this article, we present the syntax of ADML, explain its underlying semantics using the Dynamic Description Logic DDL(SHON (D)), and exemplify our approach by applying it to the domain of load balancing a wireless remote-access system;the preliminary results certify the potential of the approach.

关键词： Formal languages

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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Wear rate leveling: Lifetime enhancement of PRAM with endura...

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作者： Dong, Jianbo Zhang, Lei Han, Yinhe Wang, Ying Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling © 2011 ACM.

关键词： Phase change memory

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Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Flex memory: Exploiting and managing abundant off-chip optic...

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作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783981080179

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency. © 2011 EDAA.

关键词： Dynamic random access storage

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

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23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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Software and hardware co-designed multi-level TLBs for chip multiprocessors

Software and hardware co-designed multi-level TLBs for chip ...

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11th IEEE International Conference on computer and Information technology, CIT 2011 and 11th IEEE International Conference on Scalable computing and Communications, SCALCOM 2011

作者： Zhang, Xiaohui Cong, Ming Chen, Guangqiang Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University Beijing China National University of Defense Technology Changsha China

ISBN: (纸本)9780769543888

Translation Lookaside Buffers ( TLBs ) have a significant impact on system performance. Numerous prior studies focus on TLBs design for uniprocessors. With the advent of chip multiprocessors (CMPs), we need a shift to TLBs for chip multiprocessors. This paper presents a software-implemented level-two TLB-SL2-TLB which is a shared level-two TLB for multiprocessors. It not only reduces the cost of TLB refill handler for every processor core, but also reduces the redundant TLB misses' cost for CMPs effectively. Today, CMPs typically employ private per-core TLBs. SL2-TLB together with the hardware TLBs make up a software-hardware co-designed multilevel TLB system which brings great benefit to system performance while avoiding changing the hardware TLB. So it is a convenient and efficient method for CMPs' TLB performance improvement. The benefit brought by SL2-TLB to SPECCPU2000 is less than that to SPECCPU2006, about 5% and 7% separately. Thereinto, the average performance improvement of SPECint 2006 reaches about 12.7%. That is because the overhead for TLB refill is small when the cache is large enough to avoid a miss as walking the page table of applications with small memory footprints. The further optimization for SL2-TLB is kept the SL2-TLB table stay in L2 cache forever by the cache locking scheme. SL2-TLB together with cache locking scheme improves the performances by over 13% for SPECint 2006. And an average performance improvement of over 7% is brought to the new emerging parallel benchmark suite- Princeton Application Repository for Shared-Memory computers (PARSEC). And all the above evaluations are done on Godson-3 processors which is the latest generation of China's most powerful microprocessor family. © 2011 IEEE.

关键词： Benchmarking

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Beyond green: Evolution to adaptability and recyclability

Beyond green: Evolution to adaptability and recyclability

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2011 IEEE/ACM International Conference on Green computing and Communications, GreenCom 2011

作者： Sun, Yuzhong Song, Ying Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769544663

In current social computing system, not only hardware but also software experiences a directly discarded mode. Such directly discarded mode may result in huge waste. The major challenge in green computing is the recyclability of the computing system. In order to address this challenge in the software field, this paper proposes a design idea of green software embodying the adaptability and recyclability. The adaptable and recyclable strategy may consist of two phases. The first one is compressing the increasingly deeper software stack;another one is keeping the functionality recycling and code reuse. The adaptability and recyclability mean automatically decomposing the complex software into several parts which are ease to be reused and automatically selecting the feasible parts for the on-writing software. And we also explore the system software design path to adaptability and recyclability in our previous work as well as in the future. © 2011 IEEE.

关键词： Software design

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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A scalable parallel ray tracing algorithm for satellite imagery

A scalable parallel ray tracing algorithm for satellite imag...

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IEEE International Conference on computer Research and Development

作者： Li, Yu-Gang Zhao, Kun Huang, Yu-Qing Qiu, Zhen-Ge Liu, Zhi-Yong Beijing Lab. of Intelligent Information Technology School of Computer Science BIT Beijing 100081 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100081 China Institute of Computing Technology Chinese Academy Sciences Beijing China

ISBN: (纸本)9781612848372

Ray-tracing, can produce high-quality images, however, the use of ray-tracing has been limited due to its high demands on computational power and memory bandwidth, especially in the case of satellite imagery. In this paper, we propose a scalable parallel ray tracing algorithm of satellite imagery on a cluster of multi-core architecture. The algorithm combines demand-driven and data-driven models in order to reduce communication on the cost of maintaining redundant data. In order to make the most of computer's parallelism and increase computational efficiency, it combines two levels of parallelisms, the TLP parallelism brought by the many core architecture and the inter-node parallelism via MPI and OpenMP. Experiment results show that the algorithm is highly scalability. © 2011 IEEE.

关键词： Satellite imagery

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An efficient and flexible task management for many cores

An efficient and flexible task management for many cores

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作者： Yuan, Nan Yu, Lei Fan, Dong-Rui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

ISBN: (纸本)9783642245671

This paper presents the design and implementation of a runtime system (named "GodRunner") on Godson-T many-core processor to support task-level parallelism efficiently and flexibly. GodRunner abstracts underlying hardware resource, providing ease-of-use programming interface. A two-grade task management mechanism is proposed to support both coarse-grained and fine-grained multithreading efficiently. Two load-balanced scheduling policies are combined flexibly in GodRunner. The software-controlled task management makes GodRunner more configurable and extensible than hard-wired ones. The experiment shows that the tasking overhead in GodRunner is as small as hundreds of cycles, which is about the hundreds of times faster than the conventional Pthread based multithreading on a SMP machine. Furthermore, our approach scales well and supports fine-grained tasks as small as 20k cycles optimally. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： computer architecture

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Green challenges to system software in data centers

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Frontiers of Materials Science 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Vajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors, both the quantity and scale of data centers grow dramatically and they bring heavy energy consumption. Researchers and engineers have applied much effort to reducing hardware energy consumption, but software is the true consumer of power and another key in making better use of energy. system software is critical to better energy utilization, because it is not only the manager of hardware but also the bridge and platform between applications and hardware. In this paper, we summarize some trends that can affect the efficiency of data centers. Meanwhile, we investigate the causes of software inefficiency. Based on these studies, major technical challenges and corresponding possible solutions to attain green system software in programmability, scalability, efficiency and software architecture are discussed. Finally, some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center,power efficient system software

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