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Design Automation Conference

作者： Jianbo Dong Lei Zhang Yinhe Han Ying Wang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling.

关键词： Phase change random access memory Writing Programming Degradation Prediction algorithms systematics Complexity theory

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Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip 11

Vertical interconnects squeezing in symmetric 3D mesh Networ...

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Asia and South Pacific Design Automation Conference

作者： Cheng Liu Lei Zhang Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424475162

Three-dimensional (3D) integration and Network-on-Chip (NoC) are both proposed to tackle the on-chip interconnect scaling problems, and extensive research efforts have been devoted to the design challenges of combining both. Through-silicon via (TSV) is considered to be the most promising technology for 3D integration, however, TSV pads distributed across planar layers occupy significant chip area and result in routing congestions. In addition, the yield of 3D integrated circuits decreased dramatically as the number of TSVs increases. For symmetric 3D mesh NoC, we observe that the TSVs' utilization is pretty low and adjacent routers rarely transmit packets via their vertical channels (i.e. TSVs) at the same time. Based on this observation, we propose a novel TSV squeezing scheme to share TSVs among neighboring router in a time division multiplex mode, which greatly improves the utilization of TSVs. Experimental results show that the proposed method can save significant TSV footprint with negligible performance overhead.

关键词： Through-silicon vias Three dimensional displays Pipelines Routing Throughput computer architecture system-on-a-chip

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An intelligent load balancing algorithm towards efficient cloud computing

An intelligent load balancing algorithm towards efficient cl...

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2011 AAAI Workshop

作者： Xu, Yang Wu, Lei Guo, Liying Chen, Zheng Yang, Lai Shi, Zhongzhi Agent-based Cooperative System Lab School of Computer Science and Engineering University of Electronic Science and Technology of China Chengdu SC 611731 China Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

ISBN: (纸本)9781577355243

MapReduce provided a novel computing model for complex job decomposition and sub-tasks management to support cloud computing with large distributed data sets. However, its performance is significantly influenced by the working data distributions over those data sets. In this paper, we put forward a novel model to balance data distribution to improve cloud computing performance in data-intensive applications, such as distributed data mining. By extending the classic MapReduce model with an agent-aid layer and abstracting working load requests for data blocks as tokens, the agents can reason from previously received tokens about where to send other tokens in order to balance the working tasks and improve system performance. Our key contribution lies in building an efficient token routing algorithm in spite of agents' unknowing to the global state of data distribution in cloud. We also built a prototype of our system, and the experimental results show that our approach can significantly improve the efficiency of cloud computing. Copyright © 2011, Association for the Advancement of Artificial Intelligence. All rights reserved.

关键词： MapReduce

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SelectCast: Scalable data aggregation scheme in wireless sensor networks

SelectCast: Scalable data aggregation scheme in wireless sen...

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IEEE INFOCOM 2011

作者： Wang, Cheng Tang, Shaojie Li, Xiang-Yang Jiang, Changjun Department of Computer Science Tongji University Shanghai China Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China Department of Computer Science Illinois Institute of Technology Chicago IL 60616 United States TNLIST School of Software Tsinghua University China

ISBN: (纸本)9781424499212

In this work, for a wireless sensor network (WSN) of n randomly placed sensors with node density λ ∈ [1, n], we study the tradeoffs between the aggregation throughput and gathering efficiency. The gathering efficiency refers to the ratio of the number of the sensors whose data have been gathered to the total number of sensors. Specifically, we design two efficient aggregation schemes, called single-hop-length (SLH) scheme and multiple-hop-length (MLH) scheme. By novelly integrating these two schemes, we theoretically prove that our protocol achieves the optimal tradeoffs, and derive the optimal aggregation throughput depending on a given threshold value (lower bound) on gathering efficiency. Particularly, we show that under the MLH scheme, for a practically important set of symmetric functions called perfectly compressible functions, including the mean, max, or various kinds of indicator functions, etc., the data from Θ(n) sensors can be aggregated to the sink at the throughput of a constant order Θ(1), implying that our MLH scheme is indeed scalable. © 2011 IEEE.

关键词： Efficiency

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JVM virtual method invoking optimization based on CAM table

JVM virtual method invoking optimization based on CAM table

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IEEE International Conference on Networking, Architecture and Storage

作者： Cai, Songsong Yang, Yongqiang Lin, Chuanwen Liu, Qi Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Dept. of Computer Science and Technology University of Science and Technology of China Hefei China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769545097

In Java programs, it needs to use the information of the method type to resolve the virtual method dynamically, which restricts the performance greatly. Currently, the solution is mainly the technique of inline caching, which can be divided into two categories: monomorphic inline caching and polymorphic inline caching. Because of the simple implementation of monomorphic inline caching, it is more commonly used, but it cannot resolve the problem of frequently seeing different types of objects at one call site. Although polymorphic inline caching can solve this problem, it is costly. This paper presents the CAM hardware table, proposes a virtual method invoking mechanism based on software and hardware co-design. It solves the problem of frequently seeing different types of objects at one call site, and does not introduce additional overhead. The experimental evaluation shows that it improves the cached hit rate from 13.3% to 76.4% and improves 16.2% performance of the virtual test;it improves the performance of SPECjvm98 by 6.4% on average. © 2011 IEEE.

关键词： Virtual reality

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A domain partition model approach to the online fault recovery of FPGA-based reconfigurable systems

A domain partition model approach to the online fault recove...

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作者： Shang, Lihong Zhou, Mi Hu, Yu Yang, Erfu School of Computer Science and Engineering Beihang University Beijing 100191 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Department of Electronic and Electrical Engineering University of Strathclyde Glasgow Gl 1XW United Kingdom

Field programmable gate arrays (FPGAs) are widely used in reliability-critical systems due to their reconfiguration ability. However, with the shrinking device feature size and increasing die area, nowadays FPGAs can be deeply affected by the errors induced by electromigration and radiation. To improve the reliability of FPGA-based reconfigurable systems, a permanent fault recovery approach using a domain partition model is proposed in this paper. In the proposed approach, the fault-tolerant FPGA recovery from faults is realized by reloading a proper configuration from a pool of multiple alternative configurations with overlaps. The overlaps are presented as a set of vectors in the domain partition model. To enhance the reliability, a technical procedure is also presented in which the set of vectors are heuristically filtered so that the corresponding small overlaps can be merged into big ones. Experimental results are provided to demonstrate the effectiveness of the proposed approach through applying it to several benchmark circuits. Compared with previous approaches, the proposed approach increased MTTF by up to 18.87%. Copyright © 2011 The institute of Electronics, Information and Communication Engineers.

关键词： Fault tolerance

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Computation Pattern Driven Reuse of Manual Optimizations for GPGPUs

Computation Pattern Driven Reuse of Manual Optimizations for...

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Shixiong Xu Dongni Han Li Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences Beijing China

The wide application of General Purpose Graphic Processing Units (GPGPUs) results in large manual efforts on porting and optimizing algorithms on them. However, most existing automatic ways of generating GPGPU code fail to conduct optimization strategies regarding a specific computation and to reuse constantly evolving manual optimizations. In this paper, we present a computation pattern driven approach for computation-specific GPGPU code generation and optimization, which in turn reuses manual optimizations to a certain extent. We suggest language extensions to OpenMP, high-level data structure attributes, in order to assist the process of computation pattern matching and to help give users intuitive performance tuning parameters in the view of data structure attributes. We illustrate the feasibility of this approach through three important computation dwarfs, which are dense matrix, sparse matrix, and structured mesh computation in scientific computing. We also build a prototype OpenMP-to-CUDA translator that consists of computation pattern recognition and code template instantiation. The experimental results demonstrate the performance benefits of computation pattern driven method. To our best knowledge, it is the first work on reusing manual optimizations for GPGPUs with computation pattern driven approach.

关键词： Data structures Optimization Pattern matching Sparse matrices Manuals Libraries Tuning

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A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

A SAT-Based Pattern Generation Method for Diagnosis Multiple...

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2011 2nd International Conference on Advanced Measurement and Test (AMT 2011)

作者： Fei Wang Da Wang Haigang Yang System on Programmable Chip Research Department Institute of Electronics Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Scan chain design is a widely used design-for-testability(DFT) technique to improve test and diagnosis qualityHowever, failures on scan chain itself account for up to 30% of chip failuresTo diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvementsAs the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysisIn this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faultsThe proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolutionMoreover, the computation overhead of proving equivalent faults is reducedExperimental results on ISCAS'89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

关键词： scan chain,testing,diagnosis,boolean satisfiability(SAT),very large scale integration

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A computer-supported collaborative learning platform based on clouds

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Journal of Computational Information systems 2011年第11期7卷 3811-3818页

作者： Li, Jiandun Peng, Junjie Zhang, Wu Han, Fangfang Yuan, Qin Joint Lab of Cloud Computing School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

computer-supported collaborative learning (CSCL) is an emerging branch of learning science concerned with studying how people can learn together with the help of computers. As an indispensable ingredient, computer mediation evolves through couples of phases, e.g. centralized server, peer-to-peer network, grid computing. Nevertheless, with daily rising trend on requirement's dynamic changes in service, existing models fall short to respond on demand. Thus, in this paper, by taking advantage of cloud computing, we propose a feasible CSCL platform and the experiments show that it can not only fulfill the basic requirement of CSCL, but also respond to learner's dynamic need on demand. Copyright © 2011 Binary Information Press.

关键词： Peer to peer networks

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A scheduling algorithm for private clouds

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Journal of Convergence Information technology 2011年第7期6卷 1-9页

作者： Li, Jiandun Peng, Junjie Zhang, Wu School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing 100190 China

In contrast with public clouds, private clouds have some unique features, especially when related to workflow scheduling. Of course, the tradeoff problem between power and performance remains to be one of the key concerns. Based on our previous research, in this paper, we propose a hybrid energy-efficient scheduling algorithm using dynamic migration. The experiments show that it can not only reduce the response time, conserve more energy, but also achieve higher level of load balancing.

关键词： Scheduling algorithms

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