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Lightweight Task-Oriented Semantic Communication Empowered by Large-Scale AI Models

IEEE Transactions on Vehicular technology 2025年

作者： Liu, Chuanhong Guo, Caili Yang, Yang Chen, Mingzhe Quek, Tony Q. S. Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence School of Information and Communication Engineering Beijing100876 China Beijing University of Posts and Telecommunications Beijing Laboratory of Advanced Information Networks School of Information and Communication Engineering Beijing100876 China University of Miami Department of Electrical and Computer Engineering Institute for Data Science and Computing Coral GablesFL United States Singapore University of Technology and Design Dept. of Information Systems Technology and Design 487372 Singapore

Recent studies have focused on leveraging large-scale artificial intelligence (LAI) models to improve semantic representation and compression capabilities. However, the substantial computational demands of LAI models pose significant challenges for real-time communication scenarios. To address this, this paper proposes utilizing knowledge distillation (KD) techniques to extract and condense knowledge from LAI models, effectively reducing model complexity and computation latency. Nevertheless, the inherent complexity of LAI models leads to prolonged inference times during distillation, while their lack of channel awareness compromises the distillation performance. These limitations make standard KD methods unsuitable for task-oriented semantic communication scenarios. To address these issues, we propose a fast distillation method featuring a pre-stored compression mechanism that eliminates the need for repetitive inference, significantly improving efficiency. Furthermore, a channel adaptive module is incorporated to dynamically adjust the transmitted semantic information based on varying channel conditions, enhancing communication reliability and adaptability. In addition, an information bottleneck-based loss function is derived to guide the fast distillation process. Simulation results verify that the proposed scheme outperform baselines in term of task accuracy, model size, computation latency, and training data requirements. © 1967-2012 IEEE.

关键词： NP-hard

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A Robust key Exchange and Tamper-Resistant Protocol for HAN and NAN Networks in Smart Grids

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IEEE Internet of Things Journal 2025年

作者： Ayub, Muhammad Faizan Li, Xiong Mahmood, Khalid Shamshad, Salman Das, Ashok Kumar Wang, Guijuan University of Electronic Science and Technology of China School of Computer Science and Engineering Sichuan Chengdu611731 China National Yunlin University of Science and Technology Graduate School of Intelligent Data Science Yunlin Douliu64002 Taiwan The University of Lahore Department of Software Engineering Lahore54590 Pakistan International Institute of Information Technology Center for Security Theory and Algorithmic Research Hyderabad500 032 India Korea University College of Informatics Department of Computer Science and Engineering Anam-ro Seoul145 Korea Republic of Qilu University of Technology Shandong Academy of Sciences Key Laboratory of Computing Power Network and Information Security Ministry of Education Shandong Computer Science Center Jinan250353 China Shandong Fundamental Research Center for Computer Science Shandong Provincial Key Laboratory of Industrial Network and Information System Security Jinan250353 China

Smart Grids (SG) rely on Home Area Networks (HAN) and Neighborhood Area Networks (NAN) to ensure efficient power distribution, real-time monitoring, and seamless communication between smart devices. Despite these advantages, the use of public communication channels in HAN and NAN networks introduces critical challenges, such as vulnerability to impersonation, physical tampering, and scalability issues in resource-constrained environments. These issues compromise the stability, reliability, and security of SG environments. Existing protocols often fail to adequately address these challenges, particularly in ensuring resistance to physical tampering of supply lines and impersonation attacks. Additionally, they struggle to minimize the computation, communication, and energy costs associated with securing a resource-constrained SG environment. Therefore, we propose a robust key exchange and tamper-resistant protocol for HAN and NAN networks to address these limitations. The proposed protocol leverages the Physical Unclonable Function (PUF) mechanism to offer physical tampering resistance to smart meters. We validate our protocol formally using the Random or Real (RoR) model, which confirms its security robustness. Additionally, our informal security analysis highlights the protocol's resilience against impersonation, physical tampering attacks, etc. We analyze and compare the performance of the proposed protocol, which further demonstrates our protocol's effectiveness and security compared to competing protocols. Moreover, the proposed protocol achieves resource efficiency with 45.99% and 58.85% substantial reductions in computation overhead and energy overhead, respectively, compared to competing protocols. These results showcase the protocol's enhanced security and practicality for resource-constrained SG environments. © 2014 IEEE.

关键词： Authentication Protocol

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New Methodologies for Parallel Architecture

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Journal of computer Science & technology 2011年第4期26卷 578-587页

作者：范东睿李晓维李国杰 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences

Moore＇s law continues to grant computer architects ever more transistors in the foreseeable future, and parallelism is the key to continued performance scaling in modern microprocessors. In this paper, the achievements in our research project, which is supported by the National Basic Research 973 Program of China, on parallel architecture, are systematically presented. The innovative approaches and techniques to solve the significant problems in parallel architecture design are smnmarized, including architecture level optimization, compiler and language-supported technologies, reliability, power-performance efficient design, test and verification challenges, and platform building. Two prototype chips, a multi-heavy-core Godson-3 and a many-light-core Godson-T, are described to demonstrate the highly scalable and reconfigurable parallel architecture designs. We also present some of our achievements appearing in ISCA, MICRO, ISSCC, HPCA, PLDI, PACT, IJCAI, Hot Chips, DATE, IEEE Trans. VLSI, IEEE Micro, IEEE Trans. computers, etc.

关键词： architecture multi-core many-core parallelism

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Deterministic Circular Self Test Path

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Tsinghua Science and technology 2007年第S1期12卷 20-25页

作者：文科胡瑜李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental re- sults on ISCAS’89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.

关键词： very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic

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FaceBench: A Multi-View Multi-Level Facial Attribute VQA Dataset for Benchmarking Face Perception MLLMs

arXiv

引用

arXiv 2025年

作者： Wang, Xiaoqin Ma, Xusen Hou, Xianxu Ding, Meidan Li, Yudong Chen, Junliang Chen, Wenting Peng, Xiaoyang Shen, Linlin Computer Vision Institute College of Computer Science and Software Engineering Shenzhen University China National Engineering Laboratory for Big Data System Computing Technology Shenzhen University China Guangdong Provincial Key Laboratory of Intelligent Information Processing China AIAC Xi’an Jiaotong-Liverpool University China Tsinghua University China The Hong Kong Polytechnic University Hong Kong City University of Hong Kong Hong Kong Sun Yat-sen University China

Multimodal large language models (MLLMs) have demonstrated remarkable capabilities in various tasks. However, effectively evaluating these MLLMs on face perception remains largely unexplored. To address this gap, we introduce FaceBench, a dataset featuring hierarchical multi-view and multi-level attributes specifically designed to assess the comprehensive face perception abilities of MLLMs. Initially, we construct a hierarchical facial attribute structure, which encompasses five views with up to three levels of attributes, totaling over 210 attributes and 700 attribute values. Based on the structure, the proposed FaceBench consists of 49,919 visual question-answering (VQA) pairs for evaluation and 23,841 pairs for fine-tuning. Moreover, we further develop a robust face perception MLLM baseline, Face-LLaVA, by training with our proposed face VQA data. Extensive experiments on various mainstream MLLMs and Face-LLaVA are conducted to test their face perception ability, with results also compared against human performance. The results reveal that, the existing MLLMs are far from satisfactory in understanding the fine-grained facial attributes, while our Face-LLaVA significantly outperforms existing open-source models with a small amount of training data and is comparable to commercial ones like GPT-4o and Gemini. The dataset will be released at https://***/CVI-SZU/FaceBench. Copyright © 2025, The Authors. All rights reserved.

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Green challenges to system software in data centers

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中国计算机科学前沿 2011年第3期5卷 353-368页

作者： Yuzhong SUN Yiqiang ZHAO Ying SONG Yajun YANG Haifeng FANG Hongyong ZANG Yaqiong LI Yunwei GAO Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100190 China

With the increasing demand and the wide application of high performance commodity multi-core processors,both the quantity and scale of data centers grow dramatically and they bring heavy energy *** and engineers have applied much effort to reducing hardware energy consumption,but software is the true consumer of power and another key in making better use of *** software is critical to better energy utilization,because it is not only the manager of hardware but also the bridge and platform between applications and *** this paper,we summarize some trends that can affect the efficiency of data ***,we investigate the causes of software *** on these studies,major technical challenges and corresponding possible solutions to attain green system software in programmability,scalability,efficiency and software architecture are ***,some of our research progress on trusted energy efficient system software is briefly introduced.

关键词： green software multi-core data center power efficient system software

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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Journal of computer Science & technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

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Landing Stencil Code on Godson-T

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Journal of computer Science & technology 2010年第4期25卷 886-894页

作者：崔慧敏王蕾范东睿冯晓兵 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

The advent of multi-core/many-core chip technology offers both an extraordinary opportunity and a profound challenge. In particular, computer architects and system software designers are faced with a unique opportunity to introducing new architecture features as well as adequate compiler technology -- together they may have profound impact. This paper presents a case study （using the 1-D Jacobi computation） of compiler-amendable performance optimization techniques on a many-core architecture Godson-T. Godson-T architecture has several unique features that are chosen for this study： 1） chip-level global addressable memory in particular the scratchpad memories （SPM） local to the processing cores; 2） fine-grain memory based synchronization （e.g., full-empty bit for fine-grain synchronization）. Leveraging state-of-the-art performance optimization methods for 1-D stencil parallelization （e.g., timed tiling and variants）, we developed and implement a number of many-core-based optimization for Godson-T. Our experimental study shows good performance in both execution time speedup and scalability, validate the value of globally accessed SPM and fine-grain synchronization mechanism （full-empty bits） under the Godson-T, and provides some useful guidelines for future compiler technology of many-core chip architectures.

关键词： many-core, stencil, Jacobi, compiler SPM, fine-grain synchronization

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment

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Journal of computer Science & technology 2007年第5期22卷 673-680页

作者：王伟胡瑜韩银和李晓维张佑生 School of Computer and Information Hefei University of Technology Hefei 230009China Key Laboratory of Computer System and ArchitectureInstitute of Computing TechnologyChinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080China School of Computer and Information Hefei University of Technology Hefei 230009China

It is a well-known fact that test power consumption may exceed that during functional operation. Leakage power dissipation caused by leakage current in Complementary Metal-Oxide-Semiconductor （CMOS） circuits during test has become a significant part of the total power dissipation. Hence, it is important to reduce leakage power to prolong battery life in portable systems which employ periodic self-test, to increase test reliability and to reduce test cost. This paper analyzes leakage current and presents a kind of leakage current simulator based on the transistor stacking effect. Using it, we propose techniques based on don＇t care bits （denoted by Xs） in test vectors to optimize leakage current in integrated circuit （IC） test by genetic algorithm. The techniques identify a set of don＇t care inputs in given test vectors and reassign specified logic values to the X inputs by the genetic algorithm to get minimum leakage vector （MLV）. Experimental results indicate that the techniques can effectually optimize leakage current of combinational circuits and sequential circuits during test while maintaining high fault coverage,

关键词： leakage current don＇t care bits minimum leakage vector leakage power

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