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Pacific Rim International Symposium on Dependable computing

作者： Ying Wang Lei Zhang Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme.

关键词： Tiles Nickel Hardware Fault tolerance Fault tolerant systems Prediction algorithms computer architecture

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Improved asymptotic multicast throughput for random extended networks

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computer Communications 2010年第18期33卷 2195-2202页

作者： Cheng Wang Changjun Jiang Xiang-Yang Li Jiujun Cheng Department of Computer Science and Technology Tongji University Shanghai China State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications China Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China Department of Computer Science Illinois Institute of Technology Chicago IL 60616 USA

We study the asymptotic throughput for random extended networks , where n ad hoc nodes are randomly deployed in a square region R ( n ) = 0 , n 2 . We directly consider the multicast throughput to unify the unicast and broadcast throughput, and design a new multicast scheme under the generalized physical model based on the so-called secondary highways system . Taking account of all possible cases of n s = ω (1) and 1 ⩽ n d ⩽ n − 1, we derive the achievable multicast throughput, where n s and n d denote the number of sessions and the number of destinations of each session. We prove that for some cases in terms of n s and n d , our scheme achieves better throughput than the existing schemes.

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nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

nGFSIM : A GPU-based fault simulator for 1-to-n detection an...

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IEEE International Test Conference

作者： Huawei Li Dawen Xu Yinhe Han Kwang-Ting Cheng Xiaowei Li Department of Electrical and Computer Engineering University of California Santa Barbara USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the fault coverage of one-to n-detection for any specified integer n using only a single run of fault simulation. nGFSIM, which explores the massive parallelism in the GPU architecture and optimizes the memory access and usage, enables accelerated fault simulation without the need of fault dropping. We show that nGFSIM offers a 25X speedup in comparison with a commercial tool and enables new applications in test selection.

关键词： Circuit faults Graphics processing unit Integrated circuit modeling Instruction sets Logic gates Computational modeling Kernel

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Graph partition based path selection for testing of small delay defects 10

Graph partition based path selection for testing of small de...

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Asia and South Pacific Design Automation Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781605588377

Critical path selection plays an important role in testing of small delay defects (SDD). For some timing-balanced circuits, the numbers of candidate critical paths may be very large, and this will make Monte Carlo simulation based statistical timing analysis very inefficient. A fast path selection approach based on graph partition is proposed in this paper. First, a critical path graph (CPG) is generated to implicitly enumerate almost all candidate critical paths, and then the CPG is partitioned into several sub graphs which contain limited numbers of paths using two graph partition approaches. After that, Monte Carlo simulation is applied on each sub graph for path selection. At last, according to the partition topology of the CPG and path sets selected from each sub graph, a path set for the original CPG is generated using Union and Cartesian product operations for testing SDDs. Experimental results show that for circuits containing large numbers of candidate critical paths, the proposed path selection approach can reduce the CPU time significantly and maintain a higher probability of capturing delay failures compared to path selection methods based on general Monte Carlo simulation.

关键词： Timing Circuit testing Delay effects Sampling methods Monte Carlo methods Crosstalk system testing Laboratories Distributed computing computer architecture

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High performance comparison-based sorting algorithm on many-core GPUs

High performance comparison-based sorting algorithm on many-...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Xiaochun Ye Dongrui Fan Wei Lin Nan Yuan Paolo Ienne Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

Sorting is a kernel algorithm for a wide range of applications. In this paper, we present a new algorithm, GPU-Warpsort, to perform comparison-based parallel sort on Graphics Processing Units (GPUs). It mainly consists of a bitonic sort followed by a merge sort. Our algorithm achieves high performance by efficiently mapping the sorting tasks to GPU architectures. Firstly, we take advantage of the synchronous execution of threads in a warp to eliminate the barriers in bitonic sorting network. We also provide sufficient homogeneous parallel operations for all the threads within a warp to avoid branch divergence. Furthermore, we implement the merge sort efficiently by assigning each warp independent pairs of sequences to be merged and by exploiting totally coalesced global memory accesses to eliminate the bandwidth bottleneck. Our experimental results indicate that GPU-Warpsort works well on different kinds of input distributions, and it achieves up to 30% higher performance than previous optimized comparison-based GPU sorting algorithm on input sequences with millions of elements.

关键词： Sorting High performance computing Bandwidth Parallel architectures computer architecture Kernel Application software Multicore processing Graphics processing unit

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Integrating DBMSs as a Read-Only Execution Layer into Hadoop

Integrating DBMSs as a Read-Only Execution Layer into Hadoop

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Mingyuan An Yang Wang Weiping Wang Ninghui Sun Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China University of the Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

To obtain the efficiency of DBMS, HadoopDB combines Hadoop and DBMS, and claims the superiority over Hadoop in terms of performance. However, the approach of HadoopDB is simply putting Map Reduce onto unmodified single-machined DBMSs which has several obvious weaknesses. In essence, HadoopDB is a parallel DBMS with fault tolerance, which incurs unnecessary overhead due to the DBMS legacy. Instead of augmenting DBMS with Hadoop techniques, we propose a new system architecture integrating modified DBMS engines as a read-only execution layer into Hadoop, where DBMS plays a role of providing efficient read-only operators rather than managing the data. Besides the obtained efficiency from DBMS engine, there are other advantages. The modified DBMS engine is able to directly process data from the HDFS (Hadoop Distributed File system) files at the block level, which means that the data replication can be handled by HDFS naturally, and the block-level parallelism is easily achieved. The global index access mechanism is added according to the Map Reduce paradigm. The data loading speed is also guaranteed by directly writing the data into HDFS with simplified logic. Experiments show that our system outperforms both original Hadoop and HadoopDB styled system.

关键词： Engines Fault tolerance Fault tolerant systems Indexes Loading Parallel processing

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GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging

GVE: Godson-T Verification Engine for many-core architecture...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： Zhengmeng Lei Lunkai Zhang Fenglong Song Shibin Tang Dongrui Fan Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

In this paper, we present a Godson-T Verification Engine (GVE) to rapidly prototype and debug our Godson-T many-core processor design. GVE adopts the state-of-the-art hardware platform which contains 6 Xilinx Virtex-5 LX330 FPGAs, thus permitting us to map our many-core processor and peripheral devices into it. Besides the hardware, our toolkit Godson-T Studio provides the compiler, program loader, debugger and monitor to fulfil the purpose of developing, profiling and debugging, while the accuracy loss problem is settled by our novel techniques: Check-point and ILA-Check, presented in this paper. To our experience, GVE greatly reduces the verification cycle due to its high execution speed, for example, it finishes thousands of testcases in an hour, where the software-based approach takes few days to run. And by the help of the checkpoint framework, we can easily locate the faults. Because of these features, GVE makes a great contribution to the 16-tile Godson-T tape-out Project.

关键词： Clocks Field programmable gate arrays Synchronization Registers Hardware computer architecture Emulation

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Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagn...

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Asian Test Symposium (ATS)

作者： Jing Ye Xiaolin Zhang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguish ability are essential. However, the test patterns used by volume diagnosis commonly have low distinguish ability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fan out free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%, faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguish ability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

关键词： Circuit faults Automatic test pattern generation Benchmark testing Logic gates Transforms Integrated circuit modeling

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Trusted connection system based on virtual machine architecture

Trusted connection system based on virtual machine architect...

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International Conference on computer Science and Information technology (CSIT)

作者： Kai Zhang Ying Song Hai-feng Fang Yu-zhong Sun Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

With the rapid development of virtualization technology, virtual machine (VM) is widely used by cloud computing - the more and more popular computing paradigm. Thus, in order to guarantee the security of cloud computing, it is necessary to securely identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on. This paper designs a system of trusted connection based on virtual machine architecture and implements a system prototype. Our system not only can securely measure and identify the kernel of VM, the software stack running on VM and the hardware platform which VM relies on, but also can realize isolations to untrusted VMs. There are three main parts in our system: trusted chain, attestation and isolation. The experiments described in this paper prove that our system ensures trusted connection of VMs and achieves isolations to untrusted VMs. The performance of our system is also analyzed and evaluated. According to the analysis results, our system is practical in terms of performance.

关键词： Variable speed drives Scalability Isolators Clouds Fires

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Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power

Design of Low-Cost High-Performance Floating-Point Fused Mul...

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International Conference on VLSI Design

作者： Zichu Qi Qi Guo Ge Zhang Xiangku Li Weiwu Hu Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781424455416

This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. A modified dual-path algorithm is proposed by classifying the exponent difference into three cases and implementing them with close and far paths, which can reduce latency and facilitate lowering power consumption by enabling only one of the two paths. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve FADD instruction performance and lower power consumption. The overall FMA unit has a latency of 4 cycles while the FADD operation has 3 cycles. Each cycle has a time delay of about 0.66 ns in the ST 65 nm CMOS technology. Compared with the conventional double-precision FMA, about 13% delay is reduced and about 22% area is increased, which is acceptable since two single-precision results can be generated simultaneously.

关键词： Costs Energy consumption CMOS technology Hardware Throughput Very large scale integration Laboratories computer architecture Delay effects Roundoff errors

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