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Convergence analysis for combinatorial optimization problems based on Ito process

Journal of Computational Information systems 2010年第10期6卷 3147-3154页

作者： Yu, Ruiguo Dong, Wenyong Lei, Ming School of Computer Science and Technology Tianjin University Tianjin 300072 China Computer School Wuhan University Wuhan 430079 China Institute of Automation Chinese Acad. of Sci. Beijing 100086 China Tianjin Key Laboratory of Intelligence Computing and Novel Software Technology Tianjin University of Technology Tianjin 300191 China Key Laboratory of Computer Vision and System Ministry of Education Tianjin 300191 China

The paper provided some theoretical results about the convergence of ITO algorithm for combinatorial optimization problems. The transform probability of wave operator and move operator studied in detail. The almost sure convergence to the global optimum is obtained by transforming the search process of ITO algorithm to the discrete sub-martingale. Furthermore, the expected time of one particle in ITO algorithm is analyzed. © 2010 Binary Information Press October, 2010.

关键词： Combinatorial optimization

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Reduction Criteria for Probabilistic Models with Spatial Restrictions on States

Reduction Criteria for Probabilistic Models with Spatial Res...

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International Conference on Networks Security, Wireless Communications and Trusted computing, NSWCTC

作者： Niu Jun Guosun Zeng Embedded System and Service Computing Key Laboratory Ministry of Education Shanghai China College of Information Engineering Zhejiang Business and Technology Institute Ningbo China Department of Computer Science and Technology University of Tongji Shanghai China

ISBN: (纸本)9781424465972;9780769540115

Partial order reduction techniques have been used to combat the state explosion problem in model checking procedures for concurrent systems with probabilistic behaviors. There are some results that give criteria on applying partial order reduction for verifying quantitative time properties and reward-based properties on actions. However, there are many situations that reward-based properties are expressed on states rather than on actions because actions are triggered in no time and the quantities can not be obtained easily. This paper presents reduction criteria for a probabilistic temporal logic that allows specification of restrictions on quantitative measures given by spatial resources function for the states of the considered system and provides the proof of the correctness.

关键词： Explosions computer networks Concurrent computing Embedded computing Educational technology Probabilistic logic Communication system security computer security Information security Wireless communication

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A Generalized Model with Spatial Resources Labels

A Generalized Model with Spatial Resources Labels

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International Conference on Biomedical Engineering and computer Science (ICBECS)

This paper proposes a generalized model by extending Markov chain with spatial resources labels, which can describe the functional and performance properties and some basic characteristics such as nondeterminacy and randomicity. The syntax and semantics of the new model are shown based on the existing temporal logics such as CSRL and pathCSRL. The model checking procedure is discussed and thus the practicability of the new model is intuitive. Based on the existing models, the proposed model includes spatial resources labels only by adding the spatial information to the existing labels of states, so the treatment of the state explosion problem is similar to that in the existing models.

关键词： Educational technology Paper technology Logic Labeling Educational institutions Embedded system Embedded computing computer science education systems engineering education computer science

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P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework

P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Song Jin Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China Graduate University of Chinese Academy of Sciences Beijing P.R. China

Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime reliability analysis framework is proposed. It calibrates presilicon SSTA result by learning the collected data from path delay testing at post-silicon timing validation phase. A neural network inside P2CLRAF is trained to learn variation distribution and delay correlation based on the statistic of path delay testing. The learned information is then fed back to SSTA to further improve the accuracy of circuit lifetime reliability analysis. Experimental results demonstrate the effectiveness of the proposed analysis framework.

关键词： Lifetime Reliability Process Variation NBTI

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Design and implementation of a kind of EUPS for mobile service

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Journal of Information and Computational Science 2010年第11期7卷 2248-2257页

作者： Zhang, Xiaodan Zhang, Degan Qiao, Xiaodong Liang, Bing Peng, Hongtao Institute of Scientific and Technical Information of China Beijing 100038 China Tianjin Key Lab. of Intelligent Computing and Novel software Technology Tianjin University of Technology Tianjin 300191 China Key Laboratory of Computer Vision and System Ministry of Education Tianjin University of Technology Tianjin 300191 China Beijing Petroleum Managers Training Institute Beijing 100096 China

In order to support mobile service of long-distance monitoring and controlling UPS based on Web, a kind of design and implementation solution of embedded UPS (EUPS) system is brought forward in this paper. The design and implementation of system is based on ATmega161 and RTL8019AS with TCP/IP protocol suite for communication. In the EUPS system, an embedded file system is designed and implemented which can store the data and index information on a serial EEPROM chip in structured way and communicate with MCU through I2C bus. By embedding the file system into UPS system or other information appliances, users can browse and manipulate local data on the web client side. Based on our experimental tests, the performance of EUPS can meet the requirements of Web-based mobile services. © 2010 Binary Information Press.

关键词： Websites

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DCMTs: Supporting Dynamically Created Migratory Threads

DCMTs: Supporting Dynamically Created Migratory Threads

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IEEE International Conference on Computational Science and Engineering, CSE

作者： Yueting Zhu Wu Zhang Hai Jiang Yu Lei Junjie Peng Department of Computer Science and Engineering Shanghai University Shanghai China Department of Computer Science and Engineering University of Technology Arlington TX USA Department of Computer Science Arkansas State University Jonesboro AR USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

Thread migration is an effective technique for fault resilience and load balancing in high performance computing. However, flexible thread migration is not easy to achieve. In this paper, we present an approach to creating migratory threads dynamically at application level. The targets must be executable source files. Compared to the static ones, the number of threads created during migration with the new scheme is independent from the context. Various thread cases are considered for migration. Thread state is handled at application level. Variables are saved in structures in C language for speedy state construction. In order to solve the inability of traditional methods in tracking the created threads, a tree of active function calls is used to record the callback. The preprocessor of the proposed one is written in YACC for accuracy and programmability. The migration enabling process is transparent to programmers with the help of the preprocess. The experimental results have demonstrated the effectiveness of this approach.

关键词： Instruction sets Switches computer science Electronic mail Data preprocessing Flexible printed circuits

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SimK:A Large-Scale Parallel Simulation Engine

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Journal of computer Science & technology 2009年第6期24卷 1048-1060页

作者：许建卫陈明宇郑规曹政吕慧伟孙凝晖 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Simulation is an important method to evaluate future computer systems. Currently microprocessor architecture has switched to parallel, but almost all simulators remained at sequential stage, and the advantages brought by multi-core or many-core processors cannot be utilized. This paper presents a parallel simulator engine （SimK） towards the prevalent SMP/CMP platform, aiming at large-scale fine-grained computer system simulation. In this paper, highly efficient synchronization, communication and buffer management policies used in SimK are introduced, and a novel lock-free scheduling mechanism that avoids using any atomic instructions is presented. To deal with the load fluctuation at light load case, a cooperated dynamic task migration scheme is proposed. Based on SimK, we have developed large-scale parallel simulators HppSim and HppNetSim, which simulate a full supercomputer system and its interconnection network respectively. Results show that HppSim and HppNetSim both gain sound speedup with multiple processors, and the best normalized speedup reaches 14.95X on a two-way quad-core server.

关键词： large scale system simulation fine-grained synchronization simulation framework lock-free synchronization

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VMGuard: An Integrity Monitoring system for Management Virtual Machines

VMGuard: An Integrity Monitoring System for Management Virtu...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Haifeng Fang Yiqiang Zhao Hongyong Zang H. Howie Huang Ying Song Yuzhong Sun Zhiyong Liu University of the Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China George Washington University Washington D.C. DC USA

A cloud computing provider can dynamically allocate virtual machines (VM) based on the needs of the customers, while maintaining the privileged access to the Management Virtual Machine that directly manages the hardware and supports the guest VMs. The customers must trust the cloud providers to protect the confidentiality and integrity of their applications and data. However, as the VMs from different customers are running on the same host, an attack to the management virtual machine will easily lead to the compromise of the guest VMs. Therefore, it is critical for a cloud computing system to ensure the trustworthiness of management VMs. To this end, we propose VMGuard, an integrity monitoring and detecting system for management virtual machines in a distributed environment. VMGuard utilizes a special VM, Guard Domain, which runs on each physical node to monitor the co-resident management VMs. The integrity measurements collected by the Guard Domains are sent to the VMGuard server for safe store and independent analysis. The experimental evaluation of a Xen-based prototype shows that VMGuard can quickly detect the root kit attacks while the performance overhead is low.

关键词： Driver circuits Kernel Servers Monitoring Engines Virtual machining Area measurement

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Selected Crosstalk Avoidance Code for Reliable Network-on-Chip

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Journal of computer Science & technology 2009年第6期24卷 1074-1085页

作者：张颖李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School of the Chinese Academy of Sciences

With the shrink of the technology into nanometer scale, network-on-chip （NOC） has become a reasonable solution for connecting plenty of IP blocks on a single chip. But it suffers from both crosstalk effects and single event upset （SEU）, especially crosstalk-induced delay, which may constrain the overall performance of NOC. In this paper, we introduce a reliable NOC design using a code with the capability of both crosstalk avoidance and single error correction. Such a code, named selected crosstalk avoidance code （SCAC） in our previous work, joins crosstalk avoidance code （CAC） and error correction code （ECC） together through codeword selection from an original CAC codeword set. It can handle possible error caused by either crosstalk effects or SEU. When designing a reliable NOC, data are encoded to SCAC codewords and can be transmitted rapidly and reliably across NOC. Experimental results show that the NOC design with SCAC achieves higher performance and is reliable to tolerate single errors. Compared with previous crosstalk avoidance methods, SCAC reduces wire overhead, power dissipation and the total delay. When SCAC is used in NOC, it can save 20% area overhead and reduce 49% power dissipation.

关键词： crosstalk avoidance codeword selection reliable network-on-chip single event upset

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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