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Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors

Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...

引用

International Conference on computer and Information technology (CIT)

作者： Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency.

关键词： Hardware Software algorithms Multicore processing computer architecture Bandwidth Scalability Moore's Law Aerospace industry computer industry Software design

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Efficient binary translation system with low hardware cost

Efficient binary translation system with low hardware cost

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IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Weiwu Hu Qi Liu Jian Wang Songsong Cai Menghao Su Xiaoyu Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing architecture. The hardware supports for source-architecture-only functions, partial decodes and binary translation system acceleration are proposed. These hardware supports help the binary translation system to achieve high performance and simplify the design of the binary translation software. In the meantime, the hardware cost is well controlled in a certain low level. These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. Performance evaluations on RTL simulation and FPGA emulation platforms show that the proposed method can speedup most benchmark programs by nearly 10 times compared to pure software-based binary translation and achieves about 70% performance of the native program execution. The chip is fabricated in ST 65nm CMOS technology, and the physical design results show that the chip area cost is less than 5%.

关键词： Hardware Costs computer architecture Acceleration CMOS technology Software systems Virtual machining Decoding Software performance Field programmable gate arrays

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Column-based RLE in row-oriented database

Column-based RLE in row-oriented database

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International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC

作者： Mingyuan An Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (run-length encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage.

关键词： Database systems system performance Encoding Compression algorithms Costs Memory Engines Laboratories computer architecture Query processing

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Snooping and Ordering Ring - An Efficient Cache Coherence Protocol for Ring Connected CMP

Snooping and Ordering Ring - An Efficient Cache Coherence Pr...

引用

International Conference on Parallel and Distributed systems (ICPADS)

作者： Fei Cao Zhiyong Liu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%.

关键词： Broadcasting Bandwidth Delay Multiprocessing systems Energy consumption Access protocols Laboratories Concurrent computing Distributed computing computer architecture

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A Parallel Algorithm for computing Betweenness Centrality

A Parallel Algorithm for Computing Betweenness Centrality

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International Conference on Parallel Processing (ICPP)

作者： Guangming Tan Dengbiao Tu Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n+m) space and O((nm)/p) ( or O((nm+n 2 logn)/p)) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times.

关键词： Parallel algorithms Concurrent computing Proteins Phase change random access memory Complex networks Algorithm design and analysis Large-scale systems Parallel processing Fungi computer networks

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Early Experiences with Write-Write Design of NFS over RDMA

Early Experiences with Write-Write Design of NFS over RDMA

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Bo Li Panyong Zhang Zhigang Huo Dan Meng National Research Center for Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy of Sciences China National Research Center for Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

The network file system (NFS) protocol, as the de facto standard for sharing files in a distributed environment, has deployed Infiniband as the underlying transport of sunRPC, namely NFS over RDMA. In the current Read-Write design of NFS over RDMA, NFS write performance is limited for not fully utilizing the features of Infiniband. In this paper, we take on the challenge of enhancing the write performance of NFS. We propose and evaluate a new design of sunRPC over RDMA, namely Write-Write design. To guarantee the security of our design, we propose an HCA-based memory protection extension of Infiniband. Evaluations show that our Write-Write design increases the kernel-to-kernel RPC bandwidth by 15~27%. In real disk test, our Write-Write design gains 15%~22% in multi-client benchmarks compared with the Read-Write design.

关键词： Security Protection Bandwidth Scalability computer architecture computer networks Distributed computing File systems Benchmark testing Protocols

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Mean Shift Based Collaborative Localization with Dynamically Clustering for Wireless Sensor Networks

Mean Shift Based Collaborative Localization with Dynamically...

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WRI International Conference on Communications and Mobile computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Laboratory of Sensor Networks Chinese Academy and Sciences Beijing China

Mean shift is a nonparametric method to estimate the density gradient, which iteratively computes the mean of observations and shifts to the centroid until reach a predefined end condition. This paper proposes a mean shift based scheme for localization and tracking in wireless sensor *** shift is a generalized framework, and range-free centroid and range-based W-Centrod are both the special cases of this generalized framework. A dynamically clustering protocol is proposed to support the generalized framework. Analysis and simulation results show that the communication overhead and jitter are reduced to 1/3 of traditional algorithms. The positioning accuracy of proposed algorithm with optimal weight increases 28% and 11% in comparison to Centroid and W-Centroid.

关键词： Wireless sensor networks computer networks Clustering algorithms Laboratories Protocols Equations Mobile communication Mobile computing International collaboration computer architecture

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Smallest Enclosing Circle Based Localization Approach for Wireless Sensor Networks

Smallest Enclosing Circle Based Localization Approach for Wi...

引用

WRI International Conference on Communications and Mobile computing, CMC

作者： Quan Zhou Xiaowei Li Yongjun Xu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Laboratory of Sensor Networks Institute of Computing Technology Chinese Academy and Sciences Beijing China

A novel range-free localization approach, smallest enclosing Circle based Localization (SECL), has been proposed. This approach uses the center of smallest enclosing circle of neighboring anchor nodes to estimate the position of target. Comparing to centroid, SECL considers the geometrical coverage of anchors rather than the mass center of them. Consequently, SECL is robust to imperfect topology, especially when the topology of anchors is depolyed unevenly. Simulation results show that SECL outperforms Centroid by an average of 10%, and even better when the topology is not uniform.

关键词： Wireless sensor networks Network topology computer networks Laboratories Robustness Computational modeling Equations Hardware Mobile communication Mobile computing

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A self-repairable microprocessor

A self-repairable microprocessor

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ISTC/CSTIC 2009 (CISTC)

作者： Xie, Yuanjiang Fu, Xiang He, Zijian Zhao, Yang Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate School of Chinese Academy of Sciences Beijing 100049 China Department of Computer Science and Engineering University of California Riverside 92521 United States

ISBN: (纸本)9781615676460

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique. ©The Electrochemical Society.

关键词： Wireless sensor networks

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Characterizing Betweenness Centrality Algorithm on Multi-core Architectures

Characterizing Betweenness Centrality Algorithm on Multi-cor...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Dengbiao Tu Guangming Tan Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

This paper presents an in-depth analysis of characterization for an irregular application - computing betweenness centrality (BC) - on multicore architectures. BC algorithm is widely used in large scale graph analysis applications, which play an increasingly important role in high performance computing community. Through a joint study of architecture and application, we find that dynamically non-contiguous memory access, unstructured parallelism and low arithmetic intensity in BC program pose an obstacle to an efficient execution on parallel architectures. The experimental results report a comparison between Intel Clovertown and Sun Niagara1 for running such irregular program. Finally, several implications on multicore architecture and programming are proposed.

关键词： computer architecture Multicore processing computer applications Large-scale systems Performance analysis Algorithm design and analysis High performance computing Parallel processing Arithmetic Parallel architectures

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