检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

350 篇 会议
174 篇 期刊文献
1 册 图书

馆藏范围

525 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

336 篇 工学
- 237 篇 计算机科学与技术...
- 143 篇 软件工程
- 61 篇 电子科学与技术（可...
- 54 篇 信息与通信工程
- 52 篇 控制科学与工程
- 32 篇 机械工程
- 31 篇 电气工程
- 19 篇 生物工程
- 15 篇 光学工程
- 15 篇 材料科学与工程（可...
- 12 篇 动力工程及工程热...
- 12 篇 化学工程与技术
- 10 篇 网络空间安全
- 9 篇 交通运输工程
- 9 篇 生物医学工程（可授...
- 8 篇 仪器科学与技术
- 7 篇 建筑学
- 7 篇 土木工程
- 6 篇 冶金工程
134 篇 理学
- 70 篇 数学
- 26 篇 系统科学
- 24 篇 物理学
- 22 篇 生物学
- 14 篇 统计学（可授理学、...
- 12 篇 化学
68 篇 管理学
- 53 篇 管理科学与工程(可...
- 20 篇 工商管理
- 19 篇 图书情报与档案管...
14 篇 医学
- 12 篇 临床医学
- 10 篇 基础医学(可授医学...
5 篇 经济学
3 篇 法学
3 篇 农学
1 篇 教育学
1 篇 军事学
1 篇 艺术学

主题

56 篇 computer archite...
34 篇 laboratories
29 篇 delay
24 篇 circuit faults
22 篇 hardware
20 篇 circuit testing
20 篇 costs
19 篇 bandwidth
18 篇 clocks
16 篇 system testing
16 篇 microprocessors
15 篇 protocols
14 篇 throughput
13 篇 routing
13 篇 fault tolerance
13 篇 wireless sensor ...
13 篇 automatic test p...
13 篇 computer network...
12 篇 petri nets
12 篇 system-on-a-chip

机构

94 篇 key laboratory o...
83 篇 key laboratory o...
34 篇 institute of com...
31 篇 key laboratory o...
31 篇 graduate univers...
30 篇 national enginee...
30 篇 chinese academy ...
23 篇 key laboratory o...
19 篇 graduate univers...
18 篇 department of el...
17 篇 key laboratory o...
16 篇 chinese academy ...
16 篇 guangdong provin...
13 篇 department of el...
11 篇 department of co...
11 篇 shenzhen institu...
11 篇 university of ch...
10 篇 chinese academy ...
10 篇 loongson technol...
10 篇 school of comput...

作者

51 篇 xiaowei li
31 篇 huawei li
30 篇 zhou mengchu
25 篇 li xiaowei
22 篇 shen linlin
21 篇 yu hu
18 篇 yinhe han
17 篇 mengchu zhou
15 篇 dongrui fan
14 篇 weiwu hu
14 篇 changjun jiang
13 篇 li huawei
12 篇 cheng wang
12 篇 xiang-yang li
12 篇 hu yu
11 篇 sun ninghui
11 篇 han yinhe
10 篇 jiang changjun
9 篇 hu weiwu
9 篇 yuzhong sun

语言

471 篇 英文
29 篇 中文
25 篇 其他

检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"

共 525 条记录，以下是381-390 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Extended selective encoding of scan slices for reducing test data and test power

Extended selective encoding of scan slices for reducing test...

引用

18th Asian Test Symposium, ATS 2009

作者： Liu, Jun Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China School of Computer and Information Hefei University of Technology Hefei China Academy of Sciences Graduate University of Chinese Beijing China

ISBN: (纸本)9780769538648

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding. © 2009 IEEE.

关键词： Filling

来源：评论

学校读者我要写书评

暂无评论

An efficient methodology for power modeling and simulation of modern cell-based microprocessors

An efficient methodology for power modeling and simulation o...

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Ge Zhang Weiwu Hu Institute of Computing Technology Key Laboratory of Computer System and Architecture Beijing China

This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can be accurately estimated, and the preliminary power validation for a MIPS microprocessor proves our methodology to be effective and highly correlated, with only small errors comparing with the gate-level power analysis.

关键词： Microprocessors Circuit simulation Libraries Adders Circuit synthesis Power system modeling Analytical models Content addressable storage Power generation Flexible printed circuits

来源：评论

学校读者我要写书评

暂无评论

HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

引用

42nd Annual Simulation Symposium 2009, ANSS 2009, Part of the 2009 Spring Simulation Multiconference

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Zheng, Gui Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781617386404

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale interconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of saving simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simulation kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are introduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simulation examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

来源：评论

学校读者我要写书评

暂无评论

A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

引用

2009 16th IEEE International Conference on Electronics, Circuits and systems, ICECS 2009

作者： Qi, Zichu Liu, Hui Li, Xiangku Xu, Jun Hu, Weiwu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences PO Box 2704-25 Beijing 100190 China Beijing China Loongson Technologies Corporation Limited China

ISBN: (纸本)9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (Random Access Memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improv. The efficiency oy the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By usin. The flow, 90% transition fault coverage is achieved. In addition, bot. The number of patterns an. The test time oy the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact oy the critical paths. © 2009 IEEE.

关键词： Random access storage

来源：评论

学校读者我要写书评

暂无评论

HPPNetSim: A parallel simulation of large-scale interconnection networks

HPPNetSim: A parallel simulation of large-scale interconnect...

引用

2009 Spring Simulation Multiconference, SpringSim 2009

作者： Cao, Zheng Xu, Jianwei Chen, Mingyu Gui, Zheng Lv, Huiwei Sun, Ninghui Institute of Computing Technology Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

As the scale of parallel machine grows, communication network is playing more important role than ever before. Communication affects not only execution time, but also scalability of parallel applications. Parallel interconnection network simulator is a suitable tool to study large-scale in-terconnection networks. However, simulating packet level communication on detailed cycle-to-cycle network models is a really challenge work. We implement a kernel-based parallel simulator HPPNetSim to solve problems. Optimistic PDES mechanism needs huge memory consumption of sav-ing simulation entities' states in large-scale simulations, so we chose conservative synchronization approach. Simula-tion kernel and network models are all carefully designed. To accelerate process of simulation, optimizations are in-troduced, such as block/unblock synchronization, load balancing, dynamic look-ahead generation, and etc. Simula-tion examples and performance results show that both high accuracy and good performance are obtained in HPPNetSim. It achieves speedup of 19.8 for 32 processing nodes when simulating 36-port 3-tree fat-tree network.

关键词： Discrete event simulation

来源：评论

学校读者我要写书评

暂无评论

A New Post-Silicon Debug Approach Based on Suspect Window

A New Post-Silicon Debug Approach Based on Suspect Window

引用

IEEE VLSI Test Symposium (VTS)

作者： Jianliang Gao Yinhe Han Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

Bugs are tending to be unavoidable in the design of complex integrated circuits. It is imperative to identify the bugs as soon as possible by post-silicon debug. The main challenge for post-silicon debug is the observability of the internal signals. This paper exploits the fact that it is not necessary to observe the error free states. Then we introduce "suspect window" and present a method for determining its boundary. Based on suspect window, we propose a debug approach to achieve high observability by reusing scan chain. Since scan dumps take place only in suspect window, debug time is greatly reduced. Experimental results demonstrate the effectiveness of the proposed approach.

关键词： Post-silicon debug Suspect window Trace Scan Bug

来源：评论

学校读者我要写书评

暂无评论

Optimizing inter-domain communication

Optimizing inter-domain communication

引用

15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Zang, Hongyong Sun, Yuzhong Gu, Kuiyan Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100049 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Dongxin Geology Research Institute of Shengli Oilfield Sinopec Dongying Shandong 257094 China

ISBN: (纸本)9780769539003

Virtual machine technology has played an important role in data center. Distributed services deployed in multiple virtual machines, may reside on one physical machine. This situation requires an efficient inter-domain communication channel with transparency and security principles ensured. Although current inter-domain mechanism has gained a much better performance compared to traditional inter-domain path offered by hypervisor, shared data channel size limitation and additional copy are still two restrains against a higher performance efficiency. In this paper, we give an analysis on these limitations, overcome these shortcomings, and achieve a higher efficient inter-domain communication channel. By applying virtual address protection mechanism during channel bootstrap, we enlarge the maximum size of shared data channel. By pointing network packet structure to the buffer in the shared data channel, we avoid an extra data copy on the receiver VM side. In our evaluation using a number of standard benchmarks, we have reduced the latency by nearly 40%, increased the throughput by approximately 45% and cut down more than 3500 CPU cycles per packet. © 2009 IEEE.

关键词： Virtual machine

来源：评论

学校读者我要写书评

暂无评论

A highly efficient inter-domain communication channel

A highly efficient inter-domain communication channel

引用

IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zang, Hongyong Gu, Kuiyan Li, Yaqiong Sun, Yuzhong Meng, Dan Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University of Chinese Academy of Sciences Beijing 100049 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Dongxin Geology Research Institute of Shengli Oilfield Sinopec Dongying Shandong 257094 China

ISBN: (纸本)9780769538365

With virtual machine technology, distributed services deployed in multiple cooperative virtual machines, such as multi-tier web services, may reside on one physical machine. This situation requires an efficient inter-domain communication channel, and meanwhile transparency and security should be guaranteed, for diverse existing distributed applications are serving on plenty of machines. In this paper, we have implemented a highly efficient inter-domain communication channel, called SChannel, with full transparency to both user applications and network protocol stack, and security between guest domains on Xen platform. Between two co-resident domains, SChannel establishes a twoway shared memory channel with elastic size, which is set up using static shared memory mechanism, instead of high-cost dynamic shared memory. Furthermore, SChannel avoids one additional copy from the shared data channel on the receiver domain side. In our evaluation using a number of standard benchmarks, SChannel increases the throughput 5 times than standard inter-domain mechanism offered by the hypervisor. Compared with other typical transparent inter-domain communication mechanism, SChannel achieves approximately 44.5% improvement of throughput, and reduces more than 3500 CPU cycles per packet. © 2009 IEEE.

关键词： Transparency

来源：评论

学校读者我要写书评

暂无评论

Software and Hardware Cooperate for 1-D FFT Algorithm Optimization on Multicore Processors

Software and Hardware Cooperate for 1-D FFT Algorithm Optimi...

引用

International Conference on computer and Information technology (CIT)

作者： Yongbin Zhou Junchao Zhang Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency.

关键词： Hardware Software algorithms Multicore processing computer architecture Bandwidth Scalability Moore's Law Aerospace industry computer industry Software design

来源：评论

学校读者我要写书评

暂无评论

Efficient binary translation system with low hardware cost

Efficient binary translation system with low hardware cost

引用

IEEE International Conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Weiwu Hu Qi Liu Jian Wang Songsong Cai Menghao Su Xiaoyu Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing architecture. The hardware supports for source-architecture-only functions, partial decodes and binary translation system acceleration are proposed. These hardware supports help the binary translation system to achieve high performance and simplify the design of the binary translation software. In the meantime, the hardware cost is well controlled in a certain low level. These supports are implemented in Godson-3 processors to speedup the x86 binary translation to the native MIPS instruction set. Performance evaluations on RTL simulation and FPGA emulation platforms show that the proposed method can speedup most benchmark programs by nearly 10 times compared to pure software-based binary translation and achieves about 70% performance of the native program execution. The chip is fabricated in ST 65nm CMOS technology, and the physical design results show that the chip area cost is less than 5%.

关键词： Hardware Costs computer architecture Acceleration CMOS technology Software systems Virtual machining Decoding Software performance Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共53页 << < 35 36 37 38 39 40 41 42 43 44 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：