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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"

共 516 条记录，以下是391-400 订阅

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Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

引用

Pacific Rim International Symposium on Dependable computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

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A Low Overhead On-Chip Path Delay Measurement Circuit

A Low Overhead On-Chip Path Delay Measurement Circuit

引用

Asian Test Symposium (ATS)

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

关键词： Integrated circuit measurements Delay effects Area measurement Time measurement Delay lines Electrical fault detection Fault detection Debugging Circuit faults Added delay

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Small Delay Fault Simulation for Sequential Circuits

Small Delay Fault Simulation for Sequential Circuits

引用

Pacific Rim International Symposium on Dependable computing

作者： Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

关键词： Circuit faults Circuit simulation Sequential circuits Electrical fault detection Fault detection Propagation delay Clocks Circuit testing Inverters Automatic test pattern generation

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A Scalable Scan Architecture for Godson-3 Multicore Microprocessor

A Scalable Scan Architecture for Godson-3 Multicore Micropro...

引用

Asian Test Symposium (ATS)

作者： Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (test access mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a data-synchronous-comparator (DSC) is proposed for comparing the scan responses of the identical cores.

关键词： Multicore processing Microprocessors Switches computer architecture system testing Laboratories Large-scale systems Linear predictive coding Delay Logic testing

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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

引用

Pacific Rim International Symposium on Dependable computing

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance system recovery computer networks Region 4 Shape Laboratories computer architecture

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Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs

Efficient Physical Design Methodology for Reducing Test Powe...

引用

International Conference on Networking, Architecture, and Storage (NAS)

作者： Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China

Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circuit line. It not only can save 23% power consumption without performance loss, but also can be easily implemented with popular industrial design tools.

关键词： Design methodology Power dissipation Circuit testing Automatic test pattern generation Sequential analysis Registers computer architecture system testing Logic Controllability

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A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores

A Low-Complexity Synchronization Based Cache Coherence Solut...

引用

International Conference on computer and Information technology (CIT)

作者： Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the ldquoflagrdquo. We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included.

关键词： Protocols computer architecture Hardware Concurrent computing Costs Network-on-a-chip Coherence Tiles Information technology Helium

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Online computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures

Online Computing and Predicting Architectural Vulnerability ...

引用

Pacific Rim International Symposium on Dependable computing

作者： Songjun Pan Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft error tolerance techniques (such as redundant multithreading and instruction duplication) can achieve high fault coverage but at the cost of significant performance degradation. Prior research reports that soft errors can be masked at the architecture level, and the degree of such masking, named as architecture vulnerability factor (AVF), can vary significantly across workloads and individual structures, hence strict redundant execution may not be necessary for soft error tolerance. In this work, we exploit the AVF varying feature to adaptively tune reliability and performance. We present an infrastructure to online compute and predict AVF for three microprocessor structures (IQ, ROB, and LSQ), guiding when the protection scheme should be activated to improve reliability. Experimental results show that our method can efficiently compute the AVF for different structures independent of hardware configurations. The average differences between our method and a prior offline AVF computing method are 0.10, 0.01, and 0.039 for IQ, ROB, and LSQ, respectively.

关键词： Microprocessors Protection computer architecture Multithreading Degradation computer errors Hardware Microarchitecture Material storage Error correction codes

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Utility analysis for Internet-oriented server consolidation in VM-based data centers

Utility analysis for Internet-oriented server consolidation ...

引用

IEEE International Conference on Cluster computing

作者： Ying Song Yanwei Zhang Yuzhong Sun Weisong Shi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Wayne State University Detroit USA

Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in today's Internet-service-oriented enterprise data centers. How much power and how many servers for the underlying physical infrastructure are saved via server consolidation in VM-based data centers is of great interest to administrators and designers of those data centers. Various workload consolidations differ in saving power and physical servers for the infrastructure. The impacts caused by virtualization to those concurrent services are fluctuating considerably which may have a great effect on server consolidation. This paper proposes a utility analytic model for Internet-oriented server consolidation in VM-based data centers, modelling the interaction between server arrival requests with several QoS requirements, and capability flowing amongst concurrent services, based on the queuing theory. According to features of those services' workloads, this model can provide the upper bound of consolidated physical servers needed to guarantee QoS with the same loss probability of requests as in dedicated servers. At the same time, it can also evaluate the server consolidation in terms of power and utility of physical servers. Finally, we verify the model via a case study comprised of one e-book database service and one e-commerce Web service, simulated respectively by TPC-W and SPECweb2005 benchmarks. Our experiments show that the model is simple but accurate enough. The VM-based server consolidation saves up to 50% physical infrastructure, up to 53% power, and improves 1.7 times in CPU resource utilization, without any degradation of concurrent services' performance, running on Rainbow - our virtual computing platform.

关键词： Web server Costs Web and internet services Queueing analysis Upper bound Databases Web services Resource management Degradation Concurrent computing

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Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Variation-Aware Scheduling for Chip Multiprocessors with Thr...

引用

Pacific Rim International Symposium on Dependable computing

作者： Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can affect the performance of applications differently. Based on the above observation, we firstly formalize the variation aware scheduling in TLR-CMP as a 0-1 programming problem,to maximize the system weighted throughput. An efficient scheduling algorithm, named IntraVarF&AppSen, is then proposed to tackle this problem, which can be proved to be optimal when the number of applications to be scheduled is equal to the number of core pairs. Simulation on a 64-core CMP shows 2.8%-4% improvement in weighted throughput when compared to prior VarF&AppIPC algorithm.

关键词： Yarn Job shop scheduling Redundancy Throughput Scheduling algorithm Cathode ray tubes computer architecture Error analysis Transistors Multiprocessing systems

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