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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"
516 条 记 录,以下是391-400 订阅
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Impact of Hazards on Pattern Selection for Small Delay Defects
Impact of Hazards on Pattern Selection for Small Delay Defec...
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Pacific Rim International Symposium on Dependable computing
作者: Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test p... 详细信息
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A Low Overhead On-Chip Path Delay Measurement Circuit
A Low Overhead On-Chip Path Delay Measurement Circuit
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Asian Test Symposium (ATS)
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China
In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed... 详细信息
来源: 评论
Small Delay Fault Simulation for Sequential Circuits
Small Delay Fault Simulation for Sequential Circuits
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Pacific Rim International Symposium on Dependable computing
作者: Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is present... 详细信息
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A Scalable Scan Architecture for Godson-3 Multicore Microprocessor
A Scalable Scan Architecture for Godson-3 Multicore Micropro...
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Asian Test Symposium (ATS)
作者: Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-... 详细信息
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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes
A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...
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Pacific Rim International Symposium on Dependable computing
作者: Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty route... 详细信息
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Efficient Physical Design Methodology for Reducing Test Power Dissipation of Scan-Based Designs
Efficient Physical Design Methodology for Reducing Test Powe...
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International Conference on Networking, Architecture, and Storage (NAS)
作者: Jun Xu Xiangku Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China
Scan-based test methodology is used to resolve the sequential-test problem but suffers from high power dissipation. In this paper, we propose a scheme to prevent transitions of scan chain from reflecting into the circ... 详细信息
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A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores
A Low-Complexity Synchronization Based Cache Coherence Solut...
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International Conference on computer and Information technology (CIT)
作者: Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coheren... 详细信息
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Online computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures
Online Computing and Predicting Architectural Vulnerability ...
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Pacific Rim International Symposium on Dependable computing
作者: Songjun Pan Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Soft Errors have emerged as a key challenge to microprocessor design. Traditional soft error tolerance techniques (such as redundant multithreading and instruction duplication) can achieve high fault coverage but at t... 详细信息
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Utility analysis for Internet-oriented server consolidation in VM-based data centers
Utility analysis for Internet-oriented server consolidation ...
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IEEE International Conference on Cluster computing
作者: Ying Song Yanwei Zhang Yuzhong Sun Weisong Shi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Wayne State University Detroit USA
Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in today's Internet-service-oriented enter... 详细信息
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Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy
Variation-Aware Scheduling for Chip Multiprocessors with Thr...
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Pacific Rim International Symposium on Dependable computing
作者: Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration... 详细信息
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