检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

343 篇 会议
173 篇 期刊文献
1 册 图书

馆藏范围

517 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

331 篇 工学
- 233 篇 计算机科学与技术...
- 142 篇 软件工程
- 61 篇 电子科学与技术（可...
- 54 篇 信息与通信工程
- 49 篇 控制科学与工程
- 32 篇 机械工程
- 31 篇 电气工程
- 19 篇 生物工程
- 15 篇 材料科学与工程（可...
- 14 篇 光学工程
- 12 篇 动力工程及工程热...
- 12 篇 化学工程与技术
- 10 篇 网络空间安全
- 9 篇 交通运输工程
- 9 篇 生物医学工程（可授...
- 8 篇 仪器科学与技术
- 7 篇 建筑学
- 7 篇 土木工程
- 6 篇 冶金工程
134 篇 理学
- 70 篇 数学
- 26 篇 系统科学
- 24 篇 物理学
- 22 篇 生物学
- 14 篇 统计学（可授理学、...
- 12 篇 化学
68 篇 管理学
- 53 篇 管理科学与工程(可...
- 20 篇 工商管理
- 19 篇 图书情报与档案管...
14 篇 医学
- 12 篇 临床医学
- 10 篇 基础医学(可授医学...
5 篇 经济学
3 篇 法学
3 篇 农学
1 篇 教育学
1 篇 军事学
1 篇 艺术学

主题

56 篇 computer archite...
34 篇 laboratories
29 篇 delay
24 篇 circuit faults
22 篇 hardware
20 篇 circuit testing
20 篇 costs
19 篇 bandwidth
18 篇 clocks
16 篇 system testing
16 篇 microprocessors
15 篇 protocols
14 篇 throughput
13 篇 routing
13 篇 fault tolerance
13 篇 wireless sensor ...
13 篇 automatic test p...
13 篇 computer network...
12 篇 petri nets
12 篇 system-on-a-chip

机构

94 篇 key laboratory o...
83 篇 key laboratory o...
34 篇 institute of com...
31 篇 key laboratory o...
31 篇 graduate univers...
30 篇 chinese academy ...
26 篇 national enginee...
23 篇 key laboratory o...
19 篇 graduate univers...
18 篇 department of el...
17 篇 key laboratory o...
16 篇 chinese academy ...
13 篇 department of el...
12 篇 guangdong provin...
11 篇 department of co...
11 篇 shenzhen institu...
11 篇 university of ch...
10 篇 chinese academy ...
10 篇 loongson technol...
10 篇 school of comput...

作者

51 篇 xiaowei li
31 篇 huawei li
30 篇 zhou mengchu
25 篇 li xiaowei
21 篇 yu hu
19 篇 shen linlin
18 篇 yinhe han
17 篇 mengchu zhou
15 篇 dongrui fan
14 篇 weiwu hu
14 篇 changjun jiang
13 篇 li huawei
12 篇 cheng wang
12 篇 xiang-yang li
12 篇 hu yu
11 篇 sun ninghui
11 篇 han yinhe
10 篇 jiang changjun
9 篇 hu weiwu
9 篇 yuzhong sun

语言

468 篇 英文
29 篇 中文
20 篇 其他

检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"

共 517 条记录，以下是401-410 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Flip-Flop Selection for Transition Test Pattern Reduction Using Partial Enhanced Scan

Flip-Flop Selection for Transition Test Pattern Reduction Us...

引用

Pacific Rim International Symposium on Dependable computing

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Enhanced scan delay testing approach can achieve high transition delay fault coverage by a small size of test pattern set but with significant hardware overhead. Although the implementation cost of launch on capture (LOC) approach is relatively low, the generated pattern set for testing delay faults is typically very large. In this paper, we present a novel flip-flop selection method to combine the respective advantages of the two approaches, by replacing a small number of selected regular scan cells with enhanced scan cells, thus to reduce the overall volume of transition delay test patterns effectively. Moreover, higher fault coverage can also be obtained by this approach compared to the standard LOC approach. Experimental results on larger ISCAS-89 and ITC-99 benchmark circuits using a commercial test generation tool show that the volume of test patterns can be reduced by over 70% and the transition delay fault coverage can be improved by up to 8.7%.

关键词： Flip-flops Delay Circuit testing Lab-on-a-chip Circuit faults Test pattern generators system testing Hardware Costs Timing

来源：评论

学校读者我要写书评

暂无评论

Design of New Hash Mapping Functions

Design of New Hash Mapping Functions

引用

International Conference on computer and Information technology (CIT)

作者： Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflict-free. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewed-associative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme.

关键词： computer architecture Delay Bandwidth Costs Information technology Laboratories system-on-a-chip Hardware High performance computing Polynomials

来源：评论

学校读者我要写书评

暂无评论

Study on Fine-Grained Synchronization in Many-Core Architecture

Study on Fine-Grained Synchronization in Many-Core Architect...

引用

ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)

作者： Lei Yu Zhiyong Liu Dongrui Fan Fenglong Song Junchao Zhang Nan Yuan Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The synchronization between threads has serious impact on the performance of many-core architecture. When communication is frequent, coarse-grained synchronization brings significant overhead. Thus, coarse-grained synchronization is not suitable for this situation. However, the overhead of fine-grained synchronization is still small when the communication is frequent. For the many-core architecture which supports fine-grained synchronization with on-chip storage, we propose fine-grained synchronization algorithms for scientific computation application 2-D wavefront and LU decomposition. At first, according to the memory access mode, an efficient method of data allocation is proposed. Then, way of thread partition and synchronization are discussed. Finally, we estimate the two algorithms based on Godson-T many-core architecture. The results of experiments show that the relative speedup is almost linear and the execution time is only 53.2 % of the coarse-grained synchronization. After the global barriers are eliminated, LU decomposition achieved 13.1% performance improvement. Moreover, the experiments prove that the fine-grained mechanism is able to improve the performance of processor and it has a good scalability.

关键词： Frequency synchronization computer architecture Yarn Parallel processing Distributed computing Concurrent computing Delay Programming profession Partitioning algorithms Wire

来源：评论

学校读者我要写书评

暂无评论

Evaluation Method of Synchronization for Shared-Memory On-Chip Many-Core Processor

Evaluation Method of Synchronization for Shared-Memory On-Ch...

引用

International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Fenglong Song Zhiyong Liu Dongrui Fan He Huang Nan Yuan Lei Yu Junchao Zhang Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

On-chip many core architecture is an emerging and promising computation platform. High speed on-chip communication and abundant chipped resources are two outstanding advantages of this architecture, which provide an opportunity to implement efficient synchronization scheme. The practical execution efficiency of synchronization scheme is critical to this platform. However, there are few researches on systematic evaluation method of choice synchronization schemes for on-chip many core processors, and effect of dedicated hardware support in this context. So we focus on the evaluation method and criterion of synchronization scheme on the platform. Firstly, we present several criterions proper to on-chip many core architecture, that is, absolute overhead of synchronization operation, the transferring time between different synchronization operations, overhead caused by load imbalance, and the network congestion caused by synchronization operation. Secondly, we illustrate how to design microbenchmarks which one dedicated to evaluate a performance criterion respectively. Finally, we implement these microbenchmarks and synchronization schemes on an on-chip many core processor with shared level-two cache and AMD Opteron commercial chip multi-processor, respectively. And we analyze effect of dedicated hardware support. Results show that the most overhead of synchronization is caused by load imbalance and serialization on synchronization point. It also shows that synchronization scheme supported with dedicated hardware can improve its performance obviously for chipped many-core processor.

关键词： computer architecture Hardware Yarn Costs system-on-a-chip Concurrent computing Distributed computing Network-on-a-chip Distributed processing Application software

来源：评论

学校读者我要写书评

暂无评论

A case study of improving at-speed testing coverage of a gigahertz microprocessor

A case study of improving at-speed testing coverage of a gig...

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Zichu Qi Hui Liu Xiangku Li Jun Xu Weiwu Hu Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424450909;9781424450916

For a gigahertz microprocessor with multiple clock domains and a large amount of embedded RAMs (random access memory), generating at-speed testing patterns is becoming very difficult and very time-consuming. This paper presents some novel techniques to improve at-speed testing coverage with low cost. These methods are major concern about preventing X states propagation, which include avoiding capturing X states for registers, sequential bypass of macros, clock control scheme for inter-clock domains and accurate analysis of exception paths in intra-clock domains. Functional patterns are utilized to further improve the efficiency of the at-speed testing. A novel optimal flow is presented by carefully selecting these techniques. By using the flow, 90% transition fault coverage is achieved. In addition, both the number of patterns and the test time of the transition test are decreased by 15%. The total area overhead is about a few hundreds of AND cells and has little timing impact on the critical paths.

关键词： Microprocessors Clocks Test pattern generators system testing Costs Timing Automatic test pattern generation Delay Pattern analysis Laboratories

来源：评论

学校读者我要写书评

暂无评论

Data Management: The Spirit to Pursuit Peak Performance on Many-Core Processor

Data Management: The Spirit to Pursuit Peak Performance on M...

引用

International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Yongbin Zhou Junchao Zhang Shuai Zhang Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

To date, most of many-core prototypes employ tiled topologies connected through on-chip networks. The throughput and latency of the on-chip networks usually become to the bottleneck to achieve peak performance especially for communication intensive applications. Most of studies are focus on on-chip networks only, such as routing algorithms or router micro-architecture, to improve the above metrics. The salient aspect of our approach is that we provide a data management framework to implement high efficient on-chip traffic based on overall many-core system. The major contributions of this paper include that: (1) providing a novel tiled many-core architecture which supports software controlled on-chip data storage and movement management; (2) identifying that the asynchronous bulk data transfer mechanism is an effective method to tolerant the latency of 2-D mesh on-chip networks. At last, we evaluate the 1-D FFT algorithm on the framework and the performance achieves 47.6 Gflops with 24.8% computation efficiency.

关键词： Network-on-a-chip Delay Prototypes Network topology Throughput Routing system-on-a-chip Communication system traffic control computer architecture Memory

来源：评论

学校读者我要写书评

暂无评论

A stochastic method for controlling the scaling parameters of Cauchy mutation in fast evolutionary programming

A stochastic method for controlling the scaling parameters o...

引用

Congress on Evolutionary Computation

作者： Yunji Chen Ke Tang Tianshi Chen Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Nature Inspired Computation and Applications Laboratory Department of Computer Science and Technology University of Science and Technology of China Hefei Anhui China

The fast evolutionary programming (FEP) introduced the Cauchy distribution into its mutation operator, thus the performances of EP were promoted significantly on a number of benchmark problems. However, the scaling parameter of the Cauchy mutation is invariable, which has become an obstacle for FEP to reach better performance. This paper proposes and analyzes a new stochastic method for controlling the variable scaling parameters of Cauchy mutation. This stochastic method collects information from a group of individuals randomly selected from the population. Empirical evidence validates our method to be very helpful in promoting the performance of FEP.

关键词： Stochastic processes Genetic mutations Genetic programming Laboratories Random variables Gaussian distribution Control systems Stochastic systems computer architecture computer applications

来源：评论

学校读者我要写书评

暂无评论

Architecture Level Energy Modeling and Optimization for Multi-Ported Giga-Hz Physical Register File

Architecture Level Energy Modeling and Optimization for Mult...

引用

International Conference on Networking, Architecture, and Storage (NAS)

作者： Ge Zhang Xu Yang Yiwei Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Information and Technology University of International Relations UIR Beijing China

In modern high performance microprocessors, multi-ported register-files are commonly used and critical in both performance and energy consumption. As capability and issue width of register-file grows, its energy consumption increases rapidly. Much prior work about energy-efficient register-file design is focusing on various low levels except for architecture level. In this paper, an accurate architectural level energy model for register-file is proposed and verified, based on which some efficient and practical improvements are presented to save energy without changing the internal circuits or structure of register-file. We implemented a full-customized 64-bit width 64-entry depth physical register-file with 8 read ports and 4 write ports, whose power is as low as 20 mW, in a 1 GHz 4-issue out-of-order 64-bit MIPS microprocessor, Godson-2 [1], using 90 nm CMOS process. 56.0% of reading energy and 20.3% of writing energy can be saved.

关键词： Circuits computer architecture Energy consumption Microprocessors Registers Energy efficiency Out of order CMOS process Writing Semiconductor device modeling

来源：评论

学校读者我要写书评

暂无评论

A Highly Efficient Inter-domain Communication Channel

A Highly Efficient Inter-domain Communication Channel

引用

International Conference on computer and Information technology (CIT)

作者： Hongyong Zang Kuiyan Gu Yaqiong Li Yuzhong Sun Dan Meng Chinese Academy of Sciences Beijing China Institute of Computing Technology Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Dongxin Geology Research Institute of Shengli Oilfield Dongying Shandong China

With virtual machine technology, distributed services deployed in multiple cooperative virtual machines, such as multi-tier Web services, may reside on one physical machine. This situation requires an efficient inter-domain communication channel, and meanwhile transparency and security should be guaranteed, for diverse existing distributed applications are serving on plenty of machines. In this paper, we have implemented a highly efficient inter-domain communication channel, called SChannel, with full transparency to both user applications and network protocol stack, and security between guest domains on Xen platform. Between two co-resident domains, SChannel establishes a two-way shared memory channel with elastic size, which is set up using static shared memory mechanism, instead of high-cost dynamic shared memory. Furthermore, SChannel avoids one additional copy from the shared data channel on the receiver domain side. In our evaluation using a number of standard benchmarks, SChannel increases the throughput 5 times than standard inter-domain mechanism offered by the hypervisor. Compared with other typical transparent inter-domain communication mechanism, SChannel achieves approximately 44.5% improvement of throughput, and reduces more than 3500 CPU cycles per packet.

关键词： Communication channels Virtual machine monitors Virtual machining Protocols Throughput Hardware Data security Costs Distributed computing Physics computing

来源：评论

学校读者我要写书评

暂无评论

Detecting and Eliminating Potential Violations of Sequential Consistency for Concurrent C/C++ Programs 09

Detecting and Eliminating Potential Violations of Sequential...

引用

International Symposium on Code Generation and Optimization (CGO)

作者： Yuelu Duan Xiaobing Feng Lei Wang Chao Zhang Pen-Chung Yew Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Department of Computer Science and Engineering University of Minnesota Twin-Cities Minneapolis USA

ISBN: (纸本)9780769535760

When a concurrent shared-memory program written with a sequential consistency (SC) model is run on a machine implemented with a relaxed consistency (RC) model, it could cause SC violations that are very hard to debug. To avoid such violations, programmers need to provide explicit synchronizations or insert fence instructions. In this paper, we propose a scheme to detect and eliminate potential SC violations by combining Shasha/Snir's conflict graph and delay set theory with existing data race detection techniques. For each execution, we generate a race graph, which contains the improperly synchronized conflict accesses, called race accesses, and race cycles formed with those accesses. As a race cycle would probably lead to a non-sequential-consistent execution, we call it a potential violation of sequential consistency (PVSC) bug. We then compute the race delays of race cycles, and suggest programmers to insert fences into source code to eliminate PVSC bugs. We further convert a race graph into a PC race graph, and improves cycle detection and race delay computation to O(n 2 ), where n is the number of race access instructions. We evaluate our approach with the SPLASH-2 benchmarks, two large real-world applications (MySQL and Apache), and several multi-threaded Cilk programs. The results show that (1) the proposed approach could effec-tively detect PVSC bugs in real-world applications with good scalability; (2) it retains most of the performance of the concurrent program after inserting required fence instructions, with less than 6.3% performance loss; and (3) the additional cost of our approach over traditional race detection techniques is quite low, with 3.3% on average.

关键词： Programming profession Delay Set theory computer bugs Performance loss Chaos computer science Laboratories Concurrent computing computer architecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共52页 << < 37 38 39 40 41 42 43 44 45 46 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：