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Asian Test Symposium (ATS)

作者： Jun Liu Yinhe Han Xiaowei Li School of Computer and Information Hefei University of Technology Hefei China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don't care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding.

关键词： Encoding Circuit testing Memory Test data compression Filling Laboratories computer architecture Merging Hardware system testing

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HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs

HPP-Controller: An intra-node controller designed for connec...

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IEEE International Conference on Cluster computing

作者： Qiang Li Panyong Zhang Ninghui Sun Chinese Academy and Sciences China Chinese Academy of Sciences Beijing Beijing CN National Research Center of Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China

Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.

关键词： Joining processes Central Processing Unit Delay Bandwidth Supercomputers Petascale computing Control systems Field programmable gate arrays Access protocols Sun

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Multicast Throughput of Hybrid Wireless Networks Under Gaussian Channel Model

Multicast Throughput of Hybrid Wireless Networks Under Gauss...

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IEEE International Conference on Distributed computing systems

作者： Cheng Wang Shaojie Tang Xiang-Yang Li Changjun Jiang Yunhao Liu Department of Computer Science and Technology Tongji University Shanghai China Department of Computer Science Illinois Institute of Technology Chicago IL 60616 Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China Department of Computer Science and Engineering Hong Kong University of Science and Technology

ISBN: (纸本)9781424444816

We study the multicast capacity for hybrid wireless networks consisting of ordinary wireless nodes and base stations under Gaussian Channel model, which generalizes both the unicast capacity and broadcast capacity for hybrid wireless networks. We simply consider the hybrid extended network, where the ordinary wireless nodes are placed in the square region A(n) with side-length n~(1/2) according to a Poisson point process with unit intensity. In addition, m additional base stations (BSs) serving as the relay gateway are placed regularly in the region A(n) and they are connected by a high-bandwidth wired network. Three broad categories of multicast strategies are proposed in this paper. According to the different scenarios in terms of m, n and n_d, we select the optimal scheme from the three categories of strategies, and derive the achievable multicast throughput based on the optimal decision.

关键词： Wireless networks Multicast Gaussian channels point operation BASE STATION HYBRID Hybrid electric vehicles Throughput

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Automatic Selection of Internal Observation Signals for Design Verification

Automatic Selection of Internal Observation Signals for Desi...

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IEEE VLSI Test Symposium (VTS)

作者： Tao Lv Hua-wei Li Xiao-wei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality of functional verification. A series of formulas are defined to evaluate observability of internal signals, and an algorithm is proposed to locate the sources of low-observability. Such sources, rather than general hard-to-observe signals, are desirable internal observation signals. Experimental results indicate that signals selected by this method can improve the observability of designs more than those randomly selected from hard-to-observe signals.

关键词： Internal observation signals Design verification Static analysis

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A parallel optimization model for massive data stream application

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Ruan Jian Xue Bao/Journal of Software 2009年第SUPPL. 1期20卷 23-33页

作者： Sun, Xiao-Juan Sun, Ning-Hui Lei, Bin Key Laboratory of Technology in Geo-Spatial Information Processing and Application System Institute of Electronics The Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology The Chinese Academy of Sciences Beijing 100190 China

While computing is entering a new phase in which CPU improvements are driven by the addition of multiple cores on a single chip, rather than higher frequencies. Parallel processing on these systems is in a primitive stage, and requires the explicit use and knowledge of underlying thread architecture. Based on the features of massive data stream application, this paper proposes three-level pipelining programming model of multithreading system, which realizes the new synchronization mechanism with no contention of shared structures and is capable to provide differential service for data streams. Then the paper applies the new model to remote sensing information processing system and backbone network intrusion detection system, and evaluates the improved system on several multicore platforms. In performance analysis, the optimized effects of backbone network intrusion detection system are evaluated in several aspects of throughput scalability on both SPARC T1 and x86 platforms, the impacts of different multithreading mapping methods on throughput, and the comparison of response time and service quality before and after optimization. The experimental results show that the system throughput has good scalability on both platforms, the values of response time are greatly improved and the prioritized streams achieve better response time with the differential service mechanism. © by institute of Software, the Chinese Academy of Sciences. All rights reserved.

关键词： Metadata

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Design of a flip-flop circuit within digital logic analyzer based on FPGA

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Harbin Gongye Daxue Xuebao/Journal of Harbin institute of technology 2009年第SUPPL. 1期41卷 58-62页

作者： Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.

关键词： Field programmable gate arrays (FPGA)

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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor

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Journal of computer Science & technology 2008年第6期23卷 1037-1046页

作者：王达胡瑜李华伟李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences

This paper describes the design-for-testability （DFT） features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression structure was executed and achieved compression ratio more than ten times. Memory built-in self-test （BIST） circuitries were designed with scan collars instead of bitmaps to reduce area overheads and to improve test and debug efficiency. The implemented DFT framework also utilized internal phase-locked loops （PLL） to provide complex at-speed test clock sequences. Since there are still limitations in this DFT design, the test strategies for this case are quite complex, with complicated automatic test pattern generation （ATPG） and debugging flow. The sample testing results are given in the paper. All the DFT methods discussed in the paper are prototypes for a high-volume manufacturing （HVM） DFT plan to meet high quality test goals as well as slow test power consumption and cost.

关键词： microprocessor design-for-testability test generation built-in self-test at-speed testing

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Tradeoff cache between latency and capacity in chip multiprocessors

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第1期46卷 167-175页

作者： Xiao, Junhua Feng, Zijun Zhang, Longbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School Chinese Academy of Sciences Beijing 100049 China

Chip multiprocessors (CMP) have become the main stream microprocessor architecture. In CMP, the cache, especially the last level cache, is the critical part of its performance and becomes a focus of current research activities. CMP cache faces the conflicting requirements of satisfying both latency and capacity, and has to trade off between techniques that reduce off-chip and cross-chip misses. The private cache design minimizes the cache access latency but reduces the total effective cache capacity. The shared cache design maximizes the effective cache capacity but incurs long hit latency. In this paper, a CMP cache design (tradeoff cache between latency and capacity, TCLC) is proposed. TCLC is a private and shared hybrid design. TCLC can dynamically identify the cache blocks' shared type and optimize them respectively. The private type is optimized through migration policy, the shared read-only type is optimized through replication policy, and the shared read-write type is optimized through center placement policy. TCLC tries to make cache access latency close to private design, and effective cache capacity close to shared design, which can mitigate the impact of the wire delay and reduce the average memory access latency. The experiment results indicate that this proposal performs 13.7% better than a private cache and 12% better than a shared cache.

关键词： Economic and social effects

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Register pressure sensitive instruction speculative scheduling technology

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第3期46卷 485-491页

作者： Huang, Lei Feng, Xiaobing Lü, Fang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Speculation is an important method to overcome control flow constraints during instruction scheduling. On the one hand, speculation can exploit more instruction-level parallelism and improve performance. However, on the other hand, it may also lengthen the live range of variables and increase the register pressure, which in turn results in spilling some variables to memory and deteriorating the performance. Previous work on register pressure sensitive instruction scheduling generally scheduled instructions conservatively when there were too many live variables in the scheduling region. But actually different variables have different spilling costs and different impacts on performance. Here a register pressure sensitive speculative instruction scheduling technology is presented, which not only considers the count of live variables, but also analyzes the benefits and the spilling costs brought by instructions' speculative motions. The decrement of cycles in critical path is calculated as benefit, while the spilled variables are predicted and their spilling cost is used as cost. Only the speculative motion with benefit greater than the cost is permitted in our method. This algorithm has been implemented in Godson Compiler for MIPS architecture. Experiment result shows that the method in this paper can obtain 1.44% speedup on average relative to its register pressure insensitive counterpart on SPEC CPU2000INT benchmarks.

关键词： Costs

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Address register promotion method based on feedbacks

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第4期46卷 698-704页

作者： Zhang, Chao Lü, Fang Wang, Lei Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

In processor architectures such as MIPS, ALPHA, SPARC and PowerPC, indirect addressing mode is always adopted to access global variables and static ones. Since the addresses of these variables and the corresponding values are in different data sections in the corresponding binary file, the data locality of the program will be very poor. As a result, accessing the read only addresses of these variables every time tends to result in non-trivial redundant data cache miss memory accesses. Moreover, such indirect addressing mode will generate two sequential load instructions which have data dependences between them. As a result, the amount of instruction level parallelism (ILP) of the program will be decreased. The authors present an address register promotion method based on feedbacks (ARPF) to solve the above problems. ARPF algorithm reduces the redundant accesses to the read only addresses of the global variables and static ones, increases the amount of instruction level parallelism of a program, and avoids the performance declines due to the increase in register pressure caused by register promotion. The algorithm has been implemented in the Loongson compiler for MIPS architecture. Experiments on SPEC CPU2000INT benchmarks are conducted to show that ARPF can improve the performance of all benchmarks by 1%-6%.

关键词： Benchmarking

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