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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"
516 条 记 录,以下是411-420 订阅
排序:
Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power
Extended Selective Encoding of Scan Slices for Reducing Test...
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Asian Test Symposium (ATS)
作者: Jun Liu Yinhe Han Xiaowei Li School of Computer and Information Hefei University of Technology Hefei China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying sing... 详细信息
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HPP-Controller: An intra-node controller designed for connecting heterogeneous CPUs
HPP-Controller: An intra-node controller designed for connec...
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IEEE International Conference on Cluster computing
作者: Qiang Li Panyong Zhang Ninghui Sun Chinese Academy and Sciences China Chinese Academy of Sciences Beijing Beijing CN National Research Center of Intelligent Computing Systems Institute of Computing Technology Key Laboratory of Computer System and Architecture Chinese Academy and Sciences China
Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. I... 详细信息
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Multicast Throughput of Hybrid Wireless Networks Under Gaussian Channel Model
Multicast Throughput of Hybrid Wireless Networks Under Gauss...
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IEEE International Conference on Distributed computing systems
作者: Cheng Wang Shaojie Tang Xiang-Yang Li Changjun Jiang Yunhao Liu Department of Computer Science and Technology Tongji University Shanghai China Department of Computer Science Illinois Institute of Technology Chicago IL 60616 Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai China Department of Computer Science and Engineering Hong Kong University of Science and Technology
We study the multicast capacity for hybrid wireless networks consisting of ordinary wireless nodes and base stations under Gaussian Channel model, which generalizes both the unicast capacity and broadcast capacity for... 详细信息
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Automatic Selection of Internal Observation Signals for Design Verification
Automatic Selection of Internal Observation Signals for Desi...
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IEEE VLSI Test Symposium (VTS)
作者: Tao Lv Hua-wei Li Xiao-wei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences
As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observabilit... 详细信息
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A parallel optimization model for massive data stream application
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Ruan Jian Xue Bao/Journal of Software 2009年 第SUPPL. 1期20卷 23-33页
作者: Sun, Xiao-Juan Sun, Ning-Hui Lei, Bin Key Laboratory of Technology in Geo-Spatial Information Processing and Application System Institute of Electronics The Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Institute of Computing Technology The Chinese Academy of Sciences Beijing 100190 China
While computing is entering a new phase in which CPU improvements are driven by the addition of multiple cores on a single chip, rather than higher frequencies. Parallel processing on these systems is in a primitive s... 详细信息
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Design of a flip-flop circuit within digital logic analyzer based on FPGA
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Harbin Gongye Daxue Xuebao/Journal of Harbin institute of technology 2009年 第SUPPL. 1期41卷 58-62页
作者: Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China
With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of... 详细信息
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Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor
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Journal of computer Science & technology 2008年 第6期23卷 1037-1046页
作者: 王达 胡瑜 李华伟 李晓维 Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy of Sciences Graduate University of Chinese Academy of Sciences
This paper describes the design-for-testability (DFT) features and low-cost testing solutions of a general purpose microprocessor. The optimized DFT features are presented in detail. A hybrid scan compression struct... 详细信息
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Tradeoff cache between latency and capacity in chip multiprocessors
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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年 第1期46卷 167-175页
作者: Xiao, Junhua Feng, Zijun Zhang, Longbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School Chinese Academy of Sciences Beijing 100049 China
Chip multiprocessors (CMP) have become the main stream microprocessor architecture. In CMP, the cache, especially the last level cache, is the critical part of its performance and becomes a focus of current research a... 详细信息
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Register pressure sensitive instruction speculative scheduling technology
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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年 第3期46卷 485-491页
作者: Huang, Lei Feng, Xiaobing Lü, Fang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
Speculation is an important method to overcome control flow constraints during instruction scheduling. On the one hand, speculation can exploit more instruction-level parallelism and improve performance. However, on t... 详细信息
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Address register promotion method based on feedbacks
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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年 第4期46卷 698-704页
作者: Zhang, Chao Lü, Fang Wang, Lei Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China
In processor architectures such as MIPS, ALPHA, SPARC and PowerPC, indirect addressing mode is always adopted to access global variables and static ones. Since the addresses of these variables and the corresponding va... 详细信息
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