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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"
516 条 记 录,以下是431-440 订阅
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An interconnect-aware power efficient cache coherence protocol for CMPs
An interconnect-aware power efficient cache coherence protoc...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: Hongbo Zeng Jun Wang Ge Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The continuing shrinking of technology enables more and more processor cores to reside on a single chip. However, the power consumption and delay of global wires have presented a great challenge in designing future ch... 详细信息
来源: 评论
Location Consistency Model Revisited: Problem, Solution and Prospects
Location Consistency Model Revisited: Problem, Solution and ...
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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)
作者: Guoping Long Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Location consistency (LC) is a weak memory consistency model which is defined entirely on partial order execution semantics of parallel programs. Compared with sequential consistency (SC), LC is scalable and provides ... 详细信息
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Frequency method to study the propagation of transient fault in combinational logic
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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2008年 第5期20卷 605-611+617页
作者: Lei, Shaohua Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China
This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic. By using the Fourier transform with the input signal and the frequency feature of combina... 详细信息
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MemoryIO: An Extended I/O technology in Embedded systems
MemoryIO: An Extended I/O Technology in Embedded Systems
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International Conference on Networking, Architecture, and Storage (NAS)
作者: Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China
MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory... 详细信息
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Round-robin based scheduling algorithms for FIFO IQ switch
Round-robin based scheduling algorithms for FIFO IQ switch
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IEEE International Conference on Networking, Sensing and Control
作者: Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang Department of Computer Science and Technology University of Science and Technology China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of netwo... 详细信息
来源: 评论
Improving data availability for a cluster file system through replication
Improving data availability for a cluster file system throug...
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International Symposium on Parallel and Distributed Processing (IPDPS)
作者: Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA
Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how t... 详细信息
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Adaptive Diagnostic Pattern Generation for Scan Chains
Adaptive Diagnostic Pattern Generation for Scan Chains
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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)
作者: Fei Wang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to a... 详细信息
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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults
A design- for-diagnosis technique for diagnosing both scan c...
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Asia and South Pacific Design Automation Conference
作者: Fei Wang Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on th... 详细信息
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Testing content addressable memories using instructions and march-like algorithms
Testing content addressable memories using instructions and ...
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IEEE International Conference on Electronics, Circuits and systems (ICECS)
作者: Ma Lin Chen Yunji Su Menghao Qi Zichu Zhang Heng Hu Weiwu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approa... 详细信息
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A Scan-Based Delay Test Method for Reduction of Overtesting
A Scan-Based Delay Test Method for Reduction of Overtesting
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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)
作者: Hui Liu Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal stat... 详细信息
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