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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Hongbo Zeng Jun Wang Ge Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The continuing shrinking of technology enables more and more processor cores to reside on a single chip. However, the power consumption and delay of global wires have presented a great challenge in designing future chip multiprocessors. With these overheads of wires properly accounted for, researchers have explored some efficient on- chip network designs in the domain of larger scale caches. While in the paper, we attempt to reduce the interconnect power consumption with a novel cache coherence protocol. Conventional coherence protocols are kept independent from underlying networks for flexibility reasons. But in CMPs, processor cores and the on-chip network are tightly integrated. Exposing features of interconnect networks to protocols will unveil some optimization opportunities for power reduction. Specifically, by utilizing the location information of cores on a chip, the coherence protocol we propose in this work chooses to response the requester with the data copy in the closest sharer of the desired cache line, other than fetching it from distant L2 cache banks. This mechanism reduces the hops cache lines must travel and eliminates the power that would have incurred on the corresponding not-traveled links. To get accurate and detailed power information of interconnects, we extract wire power parameters by physical level simulation (HSPICE) and obtain router power by synthesizing RTL with actual ASIC libraries. We conduct experiments on a 16-core CMP simulator with a group of SPLASH2 benchmarks. The results demonstrate that an average of 16.3% L2 cache accesses could be optimized, resulting in an average 9.3% power reduction of data links with 19.2% as the most. This mechanism also yields a performance speedup of 1.4%.

关键词： Protocols Energy consumption Wires Network-on-a-chip Power system interconnection Delay Large-scale systems Switches Acceleration Laboratories

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Location Consistency Model Revisited: Problem, Solution and Prospects

Location Consistency Model Revisited: Problem, Solution and ...

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IEEE International Conference on Parallel and Distributed computing, Applications and Technologies (PDCAT)

作者： Guoping Long Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Location consistency (LC) is a weak memory consistency model which is defined entirely on partial order execution semantics of parallel programs. Compared with sequential consistency (SC), LC is scalable and provides ample theoretical parallelism. This makes LC an interesting memory model in the upcoming many-core parallel processing era. Previous work has pointed out that LC does not guarantee SC execution behavior for all data race free programs. In this paper, we compare the semantics of LC with PRAM consistency and memory coherence, and prove that LC is strictly weaker than PRAM consistency. For data race free programs, we prove that the semantics of LC is equivalent to memory coherence. In addition, by introducing memory ordering semantics into LC judiciously, we prove that the enhanced model is equivalent to SC for data race free programs. Finally, we discuss possible solutions for adding reasoning rules for LC-like weak memory models.

关键词： Coherence Phase change random access memory Distributed computing Parallel processing Programming profession Application software Laboratories Concurrent computing computer architecture Counting circuits

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Frequency method to study the propagation of transient fault in combinational logic

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2008年第5期20卷 605-611+617页

作者： Lei, Shaohua Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic. By using the Fourier transform with the input signal and the frequency feature of combination circuit, the output can be obtained after frequency-domain computing. A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations. Experimental results prove that our approach is several orders of magnitude faster than HSPICE, under the guarantee of approximately 93% accuracy (compared to HSPICE).

关键词： LSI circuits

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MemoryIO: An Extended I/O technology in Embedded systems

MemoryIO: An Extended I/O Technology in Embedded Systems

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Xiaojun Yang Tao Liu Fei Chen Hailiang Cheng National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Graduate University of Advanced Studies (SOKENDAI) Beijing China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyNational Research Center for Intelligent Computing Systems Chinese Academy and Sciences China

MemoryIO, a sort of extended I/O in embedded systems, is presented in this paper. MemoryIO makes it powerful for embedded systems to achieve the high-performance interconnect. In view of the facts that the main memory system is absolutely necessary in any embedded system, and not all embedded systems integrate HyperTransport (HT), PCI Express or RapidIO interface, the MemoryIO based interconnect in embedded systems has more universalities compared with that based on HT, PCI Express or RapidIO. MemoryIO can not only thoroughly compensates for the lack of high performance data transfer channel, but also efficiently utilizes the memory bus bandwidth and the direct memory access (DMA) engine to reduce the latency for data transfer in embedded systems. This paper discusses some key technologies of MemoryIO, and presents its application in DCNet and the implementation of MemoryIO IP core. The MemoryIO technology can be used in various systems, but not limited to embedded systems.

关键词： Embedded system Payloads Switches Clocks Storage area networks Physical layer Protocols

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Round-robin based scheduling algorithms for FIFO IQ switch

Round-robin based scheduling algorithms for FIFO IQ switch

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IEEE International Conference on Networking, Sensing and Control

作者： Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang Department of Computer Science and Technology University of Science and Technology China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems.

关键词： Scheduling algorithm Network-on-a-chip Telecommunication traffic Traffic control Switches Round robin Processor scheduling Delay computer networks High performance computing

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Improving data availability for a cluster file system through replication

Improving data availability for a cluster file system throug...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA

Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.

关键词： File systems Genetic mutations computer crashes Large-scale systems Availability Peer to peer computing Delay Bandwidth Laboratories computer architecture

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Adaptive Diagnostic Pattern Generation for Scan Chains

Adaptive Diagnostic Pattern Generation for Scan Chains

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Fei Wang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.

关键词： Circuit faults Electronic equipment testing system testing Application software Circuit testing Signal resolution Failure analysis Automatic test pattern generation Frequency Test pattern generators

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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

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Asia and South Pacific Design Automation Conference

作者： Fei Wang Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

关键词： Circuit faults Combinational circuits Fault diagnosis Design for disassembly Circuit testing Software testing Signal processing Flip-flops Logic Laboratories

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Testing content addressable memories using instructions and march-like algorithms

Testing content addressable memories using instructions and ...

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IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： Ma Lin Chen Yunji Su Menghao Qi Zichu Zhang Heng Hu Weiwu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

CAM is widely used in microprocessors and SOC TLB modules. It gives great advantage for software development. And TLB operations become bottleneck of the microprocessor performance. The test cost of normal BIST approach of the CAM can not be ignored. The paper analyses the fault models of CAM and proposes an instruction suitable march-like algorithm. The algorithm requires 14N+2L operations, where N is the number of words of the CAM and L is the width of a word. The algorithm covers 100% targeted faults. Instruction-level test using the algorithm has not any test cost on area and performance. Moreover the algorithm can be used in BIST approaches and have less performance lost for microprocessors. The paper instances the algorithm in a MIPS compatible microprocessor and have good results.

关键词： Associative memory computer aided manufacturing CADCAM Circuit faults Built-in self-test Circuit testing Microprocessors Costs Algorithm design and analysis Fault detection

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A Scan-Based Delay Test Method for Reduction of Overtesting

A Scan-Based Delay Test Method for Reduction of Overtesting

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Hui Liu Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing Beijing CN Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents a scan-based delay test method, called sequential-broad-side (SeBoS), to minimize overtesting of delay test. We consider two critical reasons for overtesting which are the existence of illegal states in sequential circuits and the high IR drop caused by power dissipation during structural test. The proposed SeBoS method inserts several slow clock cycles before applying the fast clock for detecting delay faults, thus considerable illegal states can be avoided and IR drop can be reduced. Illegal states are not necessarily computed before test generation. They can be accumulated and expanded during the automatic test pattern generation (ATPG) process. The derived illegal states are then used to guide test generation for the remaining faults. Compared with previous methods, the SeBoS method can avoid more illegal states when considering the same number of time frames. Experimental results on ISCAS-89 benchmark circuits show the effectiveness of the method.

关键词： Delay Circuit testing Sequential analysis Clocks Circuit faults Automatic test pattern generation Sequential circuits Power dissipation Electrical fault detection Fault detection

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