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Cache adaptive write allocate policy

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第2期44卷 348-354页

作者： Huan, Dandan Li, Zusong Hu, Weiwu Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.

关键词： Microprocessor chips

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Dependability evaluation system based on microprocessor function model

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Jisuanji Xuebao/Chinese Journal of computers 2008年第3期31卷 391-399页

作者： Zhang, Shi-Jian Xu, Tong Zhang, Long-Bing Hu, Wei-Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100039 China

With the widespread adoption of embedded microprocessor-based systems in safety critical applications, such as aircrafts, spaceships and nuclear power plants, how to rapidly and conveniently evaluate these fault-tolerant mechanisms with low cost is an important problem. The traditional method requires a detailed hardware protocol to do evaluation, which lengthens evaluation period and increases the cost. A new dependability evaluation technique based on microprocessor function model is proposed, which can evaluate fault-tolerant mechanisms more rapidly, more conveniently and more economically than the conventional systems. As a case for study, the new system evaluates three fault-tolerant techniques;the software redundancy technique, the assertion validation technique and the instruction re-fetching and re-execution technique. The results show that the evaluation is reasonable.

关键词： Fault tolerance

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Study on blocked LU decomposition on many-core architecture

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Gaojishu Tongxin/Chinese High technology Letters 2011年第3期21卷 248-253页

作者： Yu, Lei Liu, Zhiyong Ma, Yike Song, Fenglong Xu, Weizhi Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

The authors studied the scientific application LU decomposition deeply. A speedup model for LU decomposition was proposed, and an algorithm for LU decomposition based on bit reverse xor (BRX) was implemented. Then a dynamic absolute balance policy (DABP) algorithm was presented. In order to estimate the algorithms of 2 dimensional (2D) scatter, BRX and DABP, two different estimation functions were given and they were used to estimate the load balance problem of the algorithms. These two functions verify that the DABP algorithm has the best load balance. The simulations of the three algorithms were performed on the many-core architecture Godson-T. The experiments prove that the speedup of the DABP algorithm is 46 and it is the best performance of the three algorithms.

关键词： computer architecture

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Innovative architecture-level power estimation methodology for godson processor

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第5期44卷 782-789页

作者： Huang, Kun Zhang, Longbing Hu, Weiwu Zhang, Ge Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.

关键词： Microprocessor chips

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Address register promotion method based on feedbacks

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第4期46卷 698-704页

作者： Zhang, Chao Lü, Fang Wang, Lei Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

In processor architectures such as MIPS, ALPHA, SPARC and PowerPC, indirect addressing mode is always adopted to access global variables and static ones. Since the addresses of these variables and the corresponding values are in different data sections in the corresponding binary file, the data locality of the program will be very poor. As a result, accessing the read only addresses of these variables every time tends to result in non-trivial redundant data cache miss memory accesses. Moreover, such indirect addressing mode will generate two sequential load instructions which have data dependences between them. As a result, the amount of instruction level parallelism (ILP) of the program will be decreased. The authors present an address register promotion method based on feedbacks (ARPF) to solve the above problems. ARPF algorithm reduces the redundant accesses to the read only addresses of the global variables and static ones, increases the amount of instruction level parallelism of a program, and avoids the performance declines due to the increase in register pressure caused by register promotion. The algorithm has been implemented in the Loongson compiler for MIPS architecture. Experiments on SPEC CPU2000INT benchmarks are conducted to show that ARPF can improve the performance of all benchmarks by 1%-6%.

关键词： Benchmarking

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DSC: Deep scan context descriptor for large-scale place recognition

arXiv

引用

arXiv 2021年

作者： Cui, Jiafeng Huang, Tengfei Cai, Yingfeng Zhao, Junqiao Xiong, Lu Yu, Zhuoping School of Automobile Tongji University Shanghai China Department of Computer Science and Technology School of Electronics and Information Engineering Tongji University Shanghai China The Key Laboratory of Embedded System and Service Computing Ministry of Education Tongji University Shanghai China Institute of Intelligent Vehicles Tongji University Shanghai China

LiDAR-based place recognition is an essential and challenging task both in loop closure detection and global relocalization. We propose Deep Scan Context (DSC), a general and discriminative global descriptor that captures the relationship among segments of a point cloud. Unlike previous methods that utilize either semantics or a sequence of adjacent point clouds for better place recognition, we only use raw point clouds to get competitive results. Concretely, we first segment the point cloud egocentrically to acquire centroids and eigenvalues of the segments. Then, we introduce a graph neural network to aggregate these features into an embedding representation. Extensive experiments conducted on the KITTI dataset show that DSC is robust to scene variants and outperforms existing methods. © 2021, CC BY.

关键词： Eigenvalues and eigenfunctions

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CSformer: Bridging Convolution and Transformer for Compressive Sensing

arXiv

引用

arXiv 2021年

作者： Ye, Dongjie Ni, Zhangkai Wang, Hanli Zhang, Jian Wang, Shiqi Kwong, Sam The Department of Computer Science City University of Hong Kong 999077 Hong Kong The Department of Computer Science & Technology Key Laboratory of Embedded System and Service Computing Ministry of Education Shanghai Institute of Intelligent Science and Technology Tongji University Shanghai200092 China The School of Electronic and Computer Engineering Peking University Shenzhen Graduate School Shenzhen518055 China The Peng Cheng Laboratory Shenzhen518052 China The City University of Hong Kong Shenzhen Research Institute Shenzhen518057 China

Convolution neural networks (CNNs) have succeeded in compressive image sensing. However, due to the inductive bias of locality and weight sharing, the convolution operations demonstrate the intrinsic limitations in modeling the long-range dependency. Transformer, designed initially as a sequence-to-sequence model, excels at capturing global contexts due to the self-attention-based architectures even though it may be equipped with limited localization abilities. This paper proposes CSformer, a hybrid framework that integrates the advantages of leveraging both detailed spatial information from CNN and the global context provided by transformer for enhanced representation learning. The proposed approach is an end-to-end compressive image sensing method, composed of adaptive sampling and recovery. In the sampling module, images are measured block-by-block by the learned sampling matrix. In the reconstruction stage, the measurement is projected into dual stems. One is the CNN stem for modeling the neighborhood relationships by convolution, and the other is the transformer stem for adopting global self-attention mechanism. The dual branches structure is concurrent, and the local features and global representations are fused under different resolutions to maximize the complementary of features. Furthermore, we explore a progressive strategy and window-based transformer block to reduce the parameter and computational complexity. The experimental results demonstrate the effectiveness of the dedicated transformer-based architecture for compressive sensing, which achieves superior performance compared to state-of-the-art methods on different datasets. Copyright © 2021, The Authors. All rights reserved.

关键词： Compressed sensing

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Low-Light Enhancement Effect on Classification and Detection: An Empirical Study

arXiv

引用

arXiv 2024年

作者： Wu, Xu Lai, Zhihui Jie, Zhou Gao, Can Hou, Xianxu Zhang, Ya-Nan Shen, Linlin The Computer Vision Institute College of Computer Science and Software Engineering Shenzhen University Shenzhen518060 China Shenzhen Institute of Artificial Intelligence and Robotics for Society Shenzhen518060 China Guangdong Key Laboratory of Intelligent Information Processing Shenzhen University Shenzhen518060 China School of AI and Advanced Computing Xi’an Jiaotong-Liverpool University China The National Engineering Laboratory for Big Data System Computing Technology Shenzhen University SZU Branch Shenzhen Institute of Artificial Intelligence and Robotics for Society Guangdong Shenzhen518060 China

Low-light images are commonly encountered in real-world scenarios, and numerous low-light image enhancement (LLIE) methods have been proposed to improve the visibility of these images. The primary goal of LLIE is to generate clearer images that are more visually pleasing to humans. However, the impact of LLIE methods in high-level vision tasks, such as image classification and object detection, which rely on high-quality image datasets, is not well explored. To explore the impact, we comprehensively evaluate LLIE methods on these high-level vision tasks by utilizing an empirical investigation comprising image classification and object detection experiments. The evaluation reveals a dichotomy: While Low-Light Image Enhancement (LLIE) methods enhance human visual interpretation, their effect on computer vision tasks is inconsistent and can sometimes be harmful. Our findings suggest a disconnect between image enhancement for human visual perception and for machine analysis, indicating a need for LLIE methods tailored to support high-level vision tasks effectively. This insight is crucial for the development of LLIE techniques that align with the needs of both human and machine vision. Copyright © 2024, The Authors. All rights reserved.

关键词： Machine vision

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Research on rough set theory and applications in China

引用

Lecture Notes in computer Science

作者： Wang, Guoyin Zhang, Qinghua Huang, Houkuan Ye, Dongyi Hu, Qinghua Hu, Xuegang Shi, Zhongzhi Li, Yongli Shang, Lin An, Liping Sai, Ying Chen, Shanben Liang, Jiye Qin, keyun Zeng, Huanglin Xie, Keming Miao, Duoqian Min, Fan Wu, Zhaocong Wu, Weizhi Dai, Jianhua Institute of Computer Science and Technology Chongqing University of Posts and Telecommunications Chongqing 400065 China School of Information Science and Technology Southwest Jiaotong University Chengdu 610031 China School of Computer and Information Technology Beijing Jiaotong University Beijing 100044 China College of Math. and Computer Fuzhou University Fuzhou 350002 China Harbin Institute of Technology PO Box 458 Harbin 150006 China School of Computer and Information Hefei University of Technology Hefei 230009 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Lanzhou University No.222 Tianshui South Rd. Lanzhou 730000 China State Key Laboratory for Novel Software Technology Nanjing University Nanjing 210093 China Management Science and Engineering Department Business School Nankai University Tianjin 300071 China Shandong University of Finance No.40 Shun-geng Road Jinan 250014 China Welding Engineering Institute Shanghai Jiaotong University Shanghai 200030 China School of Computer and Information Technology Shanxi University Taiyuan 030006 China Intelligent Control Development Center Southwest Jiaotong University Chengdu 610031 China Artificial Intelligence of Key Laboratory Sichuan University of Science and Engineering Zigong 643000 China Department of Automation College of Information Engineering Taiyuan University of Technology Taiyuan 030024 China 4800 CaoAn Highway Shanghai 201804 China School of Computer Science and Technology University of Electronic Science and Technology of China Chengdu 610054 China School of Remote Sensing Information Engineering Wuhan University Wuhan 430079 China Institute for Information and System Sciences Faculty of Science Xi'an Jiaotong University Xi'an 710049 China Information College Zhejiang Ocean University Zhejiang 316004 China Institute of Artificial Intelligence Zhejiang University Hangzhou 310027 China

ISBN: (纸本)3540850635

This article gives a capsule view of research on rough set theory and applications ongoing at universities and laboratories in China. Included in this capsule view of rough set research is a brief description of the following things: Chinese research groups on rough set with their URLs for web pages, names of principal researchers (supervisors), numbers of graduate students, and topics being investigated. Statistical summaries showing the growth in the research on rough set theory and application in China are included. In addition, an introduction summarizing the research interests of Chinese researchers is included in this article. The contribution of this article is a complete overview of the principal research directions in rough set theory and its applications in China. © 2008 Springer-Verlag Berlin Heidelberg.

关键词： Rough set theory

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Using Data-Level Parallelism to Accelerate Instruction -Level Redundancy

Using Data-Level Parallelism to Accelerate Instruction -Leve...

引用

World Automation Congress

作者： Yu Hu Zhong liang Chen Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100190 China Department of Electrical and Computer Engineering Northeastern University Boston MA 02115 USA

ISBN: (纸本)9781467344975

Instruction-level redundancy is an effective scheme to reduce the susceptibility of microprocessors to soft errors, offering high error detection and recovery capability;however, it usually incurs significant performance degradation due to resource racing. Motivated by the fact that narrow-width operands are commonly seen in applications, we exploit data-level parallelism to accelerate instruction-level redundancy. For the instructions within sphere of replication (SoR) of data-level redundancy, normal and redundant versions of the narrow-width operand of the instruction are folded into one register to share the same functional unit during execution hence alleviating resource racing. The other instructions are all protected by instructionlevel redundancy. We run SPECint2000 benchmarks on a modified version of SimpleScalar simulator, and synthesize the extra hardware to evaluate area overhead of the proposed pipeline. Experimental results show that our acceleration scheme outperforms conventional instruction-level redundancy by 13% in IPC. Besides, the extra area overhead is negligible.

关键词： keywords Data-level redundancy Instruction-level redundancy Narrow-width value Sphere of replication

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