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Identity-Based key-Insulated Proxy Signature Without Random Oracles

Journal of Shanghai Jiaotong university(Science) 2011年第5期16卷 557-566页

作者：陈剑洪龙宇陈克非王永涛 Department of Computer Science and Engineering Shanghai Jiaotong University School of Computer Engineering Huaiyin Institute of Technology Shanghai Key Laboratory of Scalable Computing and System Shanghai Jiaotong University

In an identity based proxy signature (IBPS) scheme, a designated proxy signer can generate the signature on behalf of an original signer. Traditional IBPS schemes normally rely on the assumption that private keys are kept perfectly secure. However, due to viruses, worms or other break-ins allowed by operating-system holes, key exposure seems inevitable. To minimize the damage caused by key exposure in IBPS, we propose an identity-based key-insulated proxy signature (IBKIPS) scheme in the standard model, i.e. without random oracles.

关键词： key-insulated proxy signature identity-based standard model

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An efficient error control scheme for chip-to-chip optical interconnects

An efficient error control scheme for chip-to-chip optical i...

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2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Jun, Wang Ge, Zhang Weiwu, Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China

As the gap between processing capability and bandwidth requirement of microprocessor increases, optical interconnects are used more and more widely in chip-to-chip data links. Trade-offs are made among latency, area, power consumption and reliability in the high frequency interconnect system in which error control schemes are always implemented to make it tolerate PER (packet error rate). In this paper, a scalable system for chip-to-chip optical interconnects is proposed and different types of error control schemes are compared using 90nm CMOS process. The goals are set to low latency, small area and low power consumption as well as acceptable MTTF (mean time to failure) for USR (ultra-short-reach) with very low BER (bit error rate). After that the ECS-HC based system is picked out and validated based on FPGA and 4.25Gbps 850nm optical transceivers. © 2007 IEEE.

关键词： Error correction

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Computation pattern driven reuse of manual optimizations for GPGPUs

Computation pattern driven reuse of manual optimizations for...

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2011 12th International Conference on Parallel and Distributed computing, Applications and Technologies, PDCAT 2011

作者： Xu, Shixiong Han, Dongni Chen, Li Key Laboratory of Computer System and Architecture Institute of Computing Technology University of Chinese Beijing China

ISBN: (纸本)9780769545646

The wide application of General Purpose Graphic Processing Units (GPGPUs) results in large manual efforts on porting and optimizing algorithms on them. However, most existing automatic ways of generating GPGPU code fail to conduct optimization strategies regarding a specific computation and to reuse constantly evolving manual optimizations. In this paper, we present a computation pattern driven approach for computation-specific GPGPU code generation and optimization, which in turn reuses manual optimizations to a certain extent. We suggest language extensions to OpenMP, high-level data structure attributes, in order to assist the process of computation pattern matching and to help give users intuitive performance tuning parameters in the view of data structure attributes. We illustrate the feasibility of this approach through three important computation dwarfs, which are dense matrix, sparse matrix, and structured mesh computation in scientific computing. We also build a prototype OpenMP-to-CUDA translator that consists of computation pattern recognition and code template instantiation. The experimental results demonstrate the performance benefits of computation pattern driven method. To our best knowledge, it is the first work on reusing manual optimizations for GPGPUs with computation pattern driven approach. © 2011 IEEE.

关键词： Data structures

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A New ETL Approach Based on Data Virtualization

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Journal of computer Science & technology 2015年第2期30卷 311-323页

作者：郭树盛袁子牧孙傲冰岳强 State Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100190 China Cloud Computing Center Chinese Academy of Sciences Dongguan 523808 China

ETL （Extract-Transform-Load） usually includes three phases： extraction, transformation, and loading. In building data warehouse, it plays the role of data injection and is the most time-consuming activity. Thus it is necessary to improve the performance of ETL. In this paper, a new ETL approach, TEL （Transform-Extract-Load） is proposed. The TEL approach applies virtual tables to realize the transformation stage before extraction stage and loading stage, without data staging area or staging database which stores raw data extracted from each of the disparate source data systems. The TEL approach reduces the data transmission load, and improves the performance of query from access layers. Experimental results based on our proposed benchmarks show that the TEL approach is feasible and practical.

关键词： cloud computing big data ETL heterogeneous database data virtualization

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A Dependability Model for TMR system

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International Journal of Automation and computing 2012年第3期9卷 315-324页

作者： Peng, Jun-Jie Liu, Yan-Ping Chen, Yuan-Yuan School of Computer Engineering and Science Shanghai University Shanghai 200072 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

Much research has been done on the dependability evaluation of computer systems. However, much of this is gone no further than study of the fault coverage of such systems, with little focus on the relationship between fault coverage and overall system dependability. In this paper, a Markovian dependability model for triple-modular-redundancy (TMR) system is presented. Having fully considered the effects of fault coverage, working time, and constant failure rate of single module on the dependability of the target TMR system, the model is built based on the stepwise degradation strategy. Through the model, the relationship between the fault coverage and the dependability of the system is determined. What is more, the dependability of the system can be dynamically and precisely predicted at any given time with the fault coverage set. This will be of much benefit for the dependability evaluation and improvement, and be helpful for the system design and maintenance.

关键词： Dependability Markovian model coverage triple-modular-redundancy (TMR) failure rate.

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A parallel algorithm for computing betweenness centrality

A parallel algorithm for computing betweenness centrality

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38th International Conference on Parallel Processing, ICPP-2009

作者： Tan, Guangming Tu, Dengbiao Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769538020

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n + m) space and O(nm/p ) ( or O(nm+n2logn /p )) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times. © 2009 IEEE.

关键词： Parallel algorithms

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Software and hardware cooperate for 1-D FFT algorithm optimization on multicore processors

Software and hardware cooperate for 1-D FFT algorithm optimi...

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IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Zhou, Yongbin Zhang, Junchao Fan, Dongrui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Multicore architecture is becoming a promise to keep Moore's Law and brings a revolution in both research and industry which results new design space for software and architecture. Fast Fourier Transform (FFT), computing intensive and bandwidth intensive, is one of the most popular and important applications in the world. Compared with the computing resource on multicore architecture, the on-chip memory resource is much more expensive because of the limitation of physical chip size. Efficient implementation of FFT algorithm on multicore with good scalability is a challenge for both software and hardware developers. In this paper, supported by the Godson-T architecture, an optimized implementation of 1-D FFT has been developed with matrix transpose conceal and computation/communication overlapping, which achieve more than 30% performance improvement as well as almost 1/3 L2 cache consumption reduce comparing with the base six-step FFT. The limitation of scalability is also analyzed and the conclusion is that on Godson-T when frequency and simultaneous data access happen, the limited access bandwidth of L2 cache is the bottleneck and result in the longer on-chip network latency. © 2009 IEEE.

关键词： Fast Fourier transforms

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Circuit implementation of floating point range reduction for trigonometric functions

Circuit implementation of floating point range reduction for...

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2007 IEEE International Symposium on Circuits and systems, ISCAS 2007

作者： Xuehai, Qian Hao, Zhang Jingang, Yang He, Huang Junchao, Zhang Dongrui, Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

Range reduction is important in evaluating trigonometric functions but not enough work is done in relation to the hardware implementation of it. A hardware floating point range reduction implementation is presented. The whole reduction is divided into two steps;the first is based on Double-Residue modular range reduction method and the second adopts on a novel method described in this paper. The latter one can reduce the argument to an arbitrary range and provides the number of times that range constant contained in the argument It has been synthesized using 0.13 um library to achieve an approximately 700 MHz operation frequency. © 2007 IEEE.

关键词： Digital circuits

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Snooping and ordering ring - An efficient cache coherence protocol for ring connected CMP

Snooping and ordering ring - An efficient cache coherence pr...

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15th International Conference on Parallel and Distributed systems, ICPADS '09

作者： Cao, Fei Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China

ISBN: (纸本)9780769539003

Ring is a promising on-chip interconnection for CMP. It is more scalable than bus and much simpler than packet-switched networks. The ordering property of ring can be used to optimize cache coherence protocol design. Existing ring protocols, such as the snooping ring protocol and the ring-order protocol need a retry and acknowledgement scheme or use the ordering property of the ring respectively to resolve conflict memory requests. A cache coherence protocol named SOR (Snooping and Ordering Ring) is developed for ring connected CMP in this paper. This protocol is based on the snooping ring protocol. But instead of using the acknowledgement and retry scheme, it uses the ordering property of the ring to resolve conflicts, thus can avoid unnecessary retries to improve performance and power efficiency. The L1 snooping results are sent with the requests instead of being delayed, so that many useless snoops can be avoided. Simulation result shows that the average probe slot transports and snoop operations can be reduced by SOR are 47% and 48.9%. The average and maximum performance improvements by SOR are 3.33% and 6%. © 2009 IEEE.

关键词： Packet switching

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Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology

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Journal of computer Science & technology 2007年第1期22卷 1-14页

作者：胡伟武赵继业钟石强杨旭 Elio Guidetti 吴永强 Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China ST Microelectronics 39 Chemin du Camp-des-Filles 1228 Plan Les Ouates Geneva Switzerland

This paper introduces the microarchitecture and physical implementation of the Godson-2E processor, which is a four-issue superscalar RISC processor that supports the 64-bit MIPS instruction set. The adoption of the aggressive out-of-order execution and memory hierarchy techniques help Godson-2E to achieve high performance. The Godson-2E processor has been physically designed in a 7-metal 90nm CMOS process using the cell-based methodology with some bitsliced manual placement and a number of crafted cells and macros. The processor can be run at 1GHz and achieves a SPEC CPU2000 rate higher than 500.

关键词： general-purpose processor superscalar pipeline out-of-order execution non-blocking cache physical design,synthesis flow bit-sliced placement crafted cell performance evaluation

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