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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Xiao-Xin FAN Yu HU Laung-Temg (L.-T.) WANG Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade SynTest Technologies Inc. 505 S. Pastoria Ave. Suite 101 CA 94086 USA

To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter- clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.

关键词： Clocks Circuit testing Logic testing Automatic testing Circuit faults system testing Automatic test pattern generation Phase locked loops Automatic generation control Frequency

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Design of NIC Based on I/O Processor for Cluster Interconnect Network

Design of NIC Based on I/O Processor for Cluster Interconnec...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Xiaojun Yang Dongdong Wu Ninghui Sun National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.

关键词： computer architecture computer networks Network interfaces Supercomputers Bandwidth Intelligent systems Intelligent networks computer interfaces Power system interconnection Protocols

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NICFlex: A Functional Verification Accelerator for An RTL NIC Design

NICFlex: A Functional Verification Accelerator for An RTL NI...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： Xianyang Jiang Xiaomin Li Yue Tian Kai Wang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Chinese Academy of Sciences China

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

关键词： Acceleration Hardware Field programmable gate arrays Programmable logic arrays Time to market Network interfaces Control systems Supercomputers computer interfaces computer networks

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Shape Analysis of Volume Models by Euclidean Distance Transform and Moment Invariants

Shape Analysis of Volume Models by Euclidean Distance Transf...

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10th IEEE International Conference on computer Aided Design and computer Graphics(第十届CAO/Graphics国际会议)

作者： Dong Xu Hua Li Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese

In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.

关键词： Shape Euclidean distance Skeleton Principal component analysis Laboratories Image converters Data mining Computed tomography Clouds Iterative closest point algorithm

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Hierarchical fault tolerance memory architecture with 3-dimension interconnect

Hierarchical fault tolerance memory architecture with 3-dime...

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IEEE Region 10 International Conference TENCON

作者： Da Wang Yuanjiang Xie Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granularity redundancies and how to combine error correction code (ECC), built-in self-test (BIST), built-in repair-analysis (BIRA), and built-in self-repair (BISR) capabilities. Simulation is employed to estimate the memory behavior of various configurations, and experimental results indicate that the proposed method has substantial reliability improvements over conventional techniques. For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead. It proves the availability of the proposed architecture.

关键词： Fault tolerance Memory architecture Integrated circuit interconnections Error correction codes Integrated circuit reliability Logic circuits Built-in self-test Moore's Law CMOS technology Integrated circuit technology

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Helix Scan: A Scan Design for Diagnosis

Helix Scan: A Scan Design for Diagnosis

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第十二届全国容错计算学术会议

作者： WANG Fei HU Yu LI Xiaowei Graduate School of Chinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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Bug analysis and corresponding error models in real designs

Bug analysis and corresponding error models in real designs

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IEEE International High-Level Design Validation and Test Workshop

作者： Tao Lv Tong Xu Yang Zhao Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Microprocessor Center Department of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.

关键词： Error analysis computer bugs Microprocessors Circuit faults computer errors computer architecture Circuit testing Automatic test pattern generation Genetic mutations Laboratories

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3-D projective moment invariants

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Journal of Information and Computational Science 2007年第2期4卷 821-828页

作者： Xu, Dong Li, Hua Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Graduate University Chinese Acad. of Sci. Beijing 100080 China

2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective moment invariants are generated theoretically by investigating the property of signed volume of a tetrahedron. The main part is the selection of permutation invariant cores for multiple integrals to generate independent and nonzero 3-D projective moment invariants. We give the conclusion that projective moment invariants don't exist strictly speaking because of their convergence problem.

关键词： computer vision

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

Reliable and Energy Efficient Protocol for Wireless Sensor N...

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第十二届全国容错计算学术会议

作者： KAN Baoqiang CAI Li XU Yongjun College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer Sy College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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IEEE International Test Conference

作者： Da Wang Xiaoxin Fan Xiang Fu Hui Liu Ke Wen Rui Li Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics (Shanghai) Company Limited Shanghai China

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ... 详细信息

关键词： Microprocessors Clocks Design for testability Circuit testing Logic testing Circuit faults Manufacturing Power dissipation CMOS technology Phase locked loops

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