检索结果-内蒙古大学图书馆

Cache adaptive write allocate policy

Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第2期44卷 348-354页

作者： Huan, Dandan Li, Zusong Hu, Weiwu Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.

关键词： Microprocessor chips

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Innovative architecture-level power estimation methodology for godson processor

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第5期44卷 782-789页

作者： Huang, Kun Zhang, Longbing Hu, Weiwu Zhang, Ge Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.

关键词： Microprocessor chips

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Physical-annotation-based power modeling and estimation method for processor

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第11期19卷 1471-1475页

作者： Huang, Kun Zhang, Ge Wang, Jun Zeng, Hongbo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.

关键词： High performance processor Physical annotation Power estimation Power modeling

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An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing

An On-Chip Test Clock Control Scheme for Multi-Clock At-Spee...

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The 16th Asian Test Symposium(第十六届亚洲测试学术会议)

作者： Xiao-Xin FAN Yu HU Laung-Temg (L.-T.) WANG Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acade SynTest Technologies Inc. 505 S. Pastoria Ave. Suite 101 CA 94086 USA

To test timing-related faults between synchronous clocks, an at-speed test clock and an automatic test pattern generation scheme are needed However, previous work on designing on-chip at-speed test clock controllers for multi-clock has quadratic increasing area overhead along with linearly increasing clocks. This paper presents a clock-chain based test clock control scheme using an internal phase-locked-loop (PLL) as the at-speed test clock generator, which supports at-speed testing for inter- clock domain and intra-clock domain logic. Experimental results demonstrate that the proposed design has low area overhead when increasing the number of clocks.

关键词： Clocks Circuit testing Logic testing Automatic testing Circuit faults system testing Automatic test pattern generation Phase locked loops Automatic generation control Frequency

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Design of NIC Based on I/O Processor for Cluster Interconnect Network

Design of NIC Based on I/O Processor for Cluster Interconnec...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Xiaojun Yang Dongdong Wu Ninghui Sun National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.

关键词： computer architecture computer networks Network interfaces Supercomputers Bandwidth Intelligent systems Intelligent networks computer interfaces Power system interconnection Protocols

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NICFlex: A Functional Verification Accelerator for An RTL NIC Design

NICFlex: A Functional Verification Accelerator for An RTL NI...

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IEEE International Conference on Field-Programmable technology (FPT)

作者： Xianyang Jiang Xiaomin Li Yue Tian Kai Wang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Chinese Academy of Sciences China

A short time-to-market is very important for a chip, and verification takes the most (about 70%) of its design time. Network interface controller (NIC) is a key component for a supercomputer and other computing systems. To reduce verification time for such a market-demanding product plays a great role in relevant system design. In this paper, a functional verification accelerator NICFlex is presented for a register transfer level (RTL) NIC design. NICFlex accelerates verification process by both a software part and a hardware part. The software part runs as a simulation thread, and the hardware part is mapped into field programmable gate array (FPGA) logic together with a NIC wrapper. Compared to a conventional simulation verification method using ModelSim, NICFlex can accelerate the functional verification of an RTL NIC design for hundreds of times or more. With extension, NICFlex is promising for any functional verification acceleration of a generic RTL design.

关键词： Acceleration Hardware Field programmable gate arrays Programmable logic arrays Time to market Network interfaces Control systems Supercomputers computer interfaces computer networks

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Fault tolerant communication algorithm for network on chip

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第4期19卷 508-514页

作者： Zhang, Lei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China Advanced Test Technology Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper proposes a random routing algorithm with end-to-end feedback. Random routing has the capability of handling random transmission errors efficiently with high forwarding speed. End-to-end feedback promises the correctness of transmission and reduces the power consumption. Experimental results demonstrated that our random routing algorithm has lower latency, lower power consumption, and can provide on-chip communication with high reliability.

关键词： Error correcting and detecting Fault tolerant Flooding algorithm Network on chip Random routing Random walk Reliability

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Shape Analysis of Volume Models by Euclidean Distance Transform and Moment Invariants

Shape Analysis of Volume Models by Euclidean Distance Transf...

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10th IEEE International Conference on computer Aided Design and computer Graphics(第十届CAO/Graphics国际会议)

作者： Dong Xu Hua Li Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese

In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.

关键词： Shape Euclidean distance Skeleton Principal component analysis Laboratories Image converters Data mining Computed tomography Clouds Iterative closest point algorithm

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Hierarchical fault tolerance memory architecture with 3-dimension interconnect

Hierarchical fault tolerance memory architecture with 3-dime...

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IEEE Region 10 International Conference TENCON

作者： Da Wang Yuanjiang Xie Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper proposed hierarchical fault tolerance techniques for ultrahigh-density memories based on 3- dimension interconnect technology. It describes how to implement hierarchical architecture with different granularity redundancies and how to combine error correction code (ECC), built-in self-test (BIST), built-in repair-analysis (BIRA), and built-in self-repair (BISR) capabilities. Simulation is employed to estimate the memory behavior of various configurations, and experimental results indicate that the proposed method has substantial reliability improvements over conventional techniques. For a memory with 1% bit-level failure rate and 50% device-level defect density, the proposed method can gain 100% reliability by using less than 30% extra overhead. It proves the availability of the proposed architecture.

关键词： Fault tolerance Memory architecture Integrated circuit interconnections Error correction codes Integrated circuit reliability Logic circuits Built-in self-test Moore's Law CMOS technology Integrated circuit technology

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Helix Scan: A Scan Design for Diagnosis

Helix Scan: A Scan Design for Diagnosis

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第十二届全国容错计算学术会议

作者： WANG Fei HU Yu LI Xiaowei Graduate School of Chinese Academy of Sciences Beijing 100080China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Scan design is a widely used design-for-testability technique to improve test quality and efficiency. For the scan-designed circuit, test and diagnosis of the scan chain and the circuit is an important process for silicon debug and yield learning. However, conventional scan designs and diagnosis methods abort the subsequent diagnosis process after diagnosing the scan chain if the scan chain is faulty. In this work, we propose a design-for-diagnosis scan strategy called helix scan and a diagnosis algorithm to address this issue. Unlike previous proposed methods, helix scan has the capability to carry on the diagnosis process without losing information when the scan chain is faulty. What is more, it simplifies scan chain diagnosis and achieves high diagnostic resolution as well as accuracy. Experimental results demonstrate the effectiveness of our design.

关键词： test diagnosis scan chain diagnosis design for diagnosis (DFD)

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