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2009 International Conference on Cyber-Enabled Distributed computing and Knowledge Discovery, CyberC '09

作者： An, Mingyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424452187

In database systems, disk I/O performance is usually the bottleneck of the whole query processing. Among many techniques, compression is one of the most important ones to reduce disk accesses so to improve system performance. RLE (Run-Length Encoding) is one light-weight compression algorithm which incurs negligible CPU cost. A lot of work show that, although RLE is one of the most effective compression techniques in column-oriented systems, it is very hard to use due to bad value locality in row-oriented systems where values from multiple attributes are stored in the same page. We propose CRLE (Column-based RLE), one compression algorithm to apply RLE to row-oriented data storage. On row-oriented storage page, CRLE can exploit value locality in individual column and encode values from the same column in run-length format. Experiments show that CRLE can lead to very good compression ratio and performance in spite of row-oriented data storage. © 2009 IEEE.

关键词： Query processing

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An Efficient Threshold key-Insulated Signature Scheme

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Journal of Shanghai Jiaotong university(Science) 2011年第6期16卷 658-662页

作者：陈剑洪龙宇陈克非王永涛李祥学 Department of Computer Science and Engineering Shanghai Jiaotong University School of Computer Engineering Huaiyin Institute of Technology Shanghai Key Laboratory of Scalable Computing and System Shanghai Jiaotong University Department of Computer Science and Technology East China Normal University

To tackle the key-exposure problem in signature settings,this paper introduces a new cryptographic primitive named threshold key-insulated signature(TKIS) and proposes a concrete TKIS *** a TKIS system,at least k out of n helpers are needed to update a user's temporary private *** the one hand,even if up to k 1 helpers are compromised in addition to the exposure of any of temporary private keys,security of the non-exposed periods is still *** the other hand,even if all the n helpers are compromised,we can still ensure the security of all periods as long as none of temporary private keys is *** with traditional key-insulated signature(KIS) schemes,the proposed TKIS scheme not only greatly enhances the security of the system,but also provides flexibility and efficiency.

关键词： threshold key-insulation signature random oracle model

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Data protection and provenance in cloud of things environment: Research challenges

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International Journal of Information and computer Security 2020年第4期12卷 416-435页

作者： Wang, Chundong Yang, Lei Guo, Hao Wan, Fujin Key Laboratory of Computer Vision and System Tianjin Key Laboratory of Intelligence Computing and Novel Software Technology Ministry of Education Tianjin University of Technology Tianjin China Global Energy Internet Research Institute Beijing University of Technology Tianjin China Department of College of Computer and Control Engineering Nankai University Tianjin China

Internet of things are increasingly being deployed over the cloud (also referred to as cloud of things) to provide a broader range of services. However, there are serious challenges of CoT in the data protection and security provenance. This paper proposes a data privacy protection and provenance model (DPSPM) based on CoT. It can protect the privacy data of the users and trace the source of leaked data. In detail, security encryption and watermarking algorithms are proposed. Meanwhile, we use the improved k-anonymity data masking algorithm and pseudo-row watermarking algorithm in this scheme. Those algorithms can carry out security control over the whole process of data publishing, especially in data encryption, data masking and provenance verification. Finally, the experimental results show that our scheme has good efficiency. It is proved that the data masking time is proportional to the parameters k and L, the results also show good robustness to the common database watermarking attacks. © 2020 Inderscience Enterprises Ltd.

关键词： Data privacy

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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation

Wear rate leveling: Lifetime enhancement of PRAM with endura...

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作者： Dong, Jianbo Zhang, Lei Han, Yinhe Wang, Ying Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling © 2011 ACM.

关键词： Phase change memory

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Flex memory: Exploiting and managing abundant off-chip optical bandwidth

Flex memory: Exploiting and managing abundant off-chip optic...

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作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9783981080179

The emerging nanophotonic technology can avoid the limitation of I/O pin count, and provide abundant memory bandwidth. However, current DRAM organization has mainly been optimized for a higher storage capacity and package pin utilization. The resulted data fetching mechanism is quite inefficient in performance and energy saving, and cannot effectively utilize the abundant optical bandwidth in off-chip communication. This paper inspects the opportunity brought by optical communication, and revisits the DRAM memory architecture considering the technology trend towards multiprocessors. In our FlexMemory design, super-line prefetching is proposed to boost system performance and promote energy efficiency, which leverages the abundant photonic bandwidth to enlarge the effective data fetch size per memory cycle. To further preserve locality and maintain service parallelism for different workloads, page folding technique is employed to achieve adaptive data mapping in photonics-connected DRAM chips via optical wavelengths allocation. By combining both techniques, surplus off-chip bandwidth can be utilized and effectively managed adapting to the workloads intensity. Experimental results show that our FlexMemory achieves considerable improvements in performance and energy efficiency. © 2011 EDAA.

关键词： Dynamic random access storage

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Locality and parallelism optimization for dynamic programming algorithm in bioinformatics

Locality and parallelism optimization for dynamic programmin...

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2006 ACM/IEEE Conference on Supercomputing, SC'06

作者： Tan, Guangming Feng, Shengzhong Sun, Ninghui Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Graduate School Chinese Academy of Sciences

ISBN: (纸本)0769527000

Dynamic programming has been one of the most efficient approaches to sequence analysis and structure prediction in biology. However, their performance is limited due to the drastic increase in both the number of biological data and variety of the computer architectures. With regard to such predicament, this paper creates excellent algorithms aimed at addressing the challenges of improving memory efficiency and network latency tolerance for nonserial polyadic dynamic programming where the dependences are nonuniform. By relaxing the nonuniform dependences, we proposed a new cache oblivious scheme to enhance its performance on memory hierarchy architectures. Moreover we develop and extend a tiling technique to parallelize this nonserial polyadic dynamic programming using an alternate block-cyclic mapping strategy for balancing the computational and memory load, where an analytical parameterized model is formulated to determine the tile volume size that minimizes the total execution time and an algorithmic transformation is used to schedule the tile to overlap communication with computation to further minimize communication overhead on parallel architectures. The numerical experiments were carried out on several high performance computer systems. The new cache-oblivious dynamic programming algorithm achieve 2-10 speedup and the parallel tiling algorithm with communication-computation overlapping shows a desired potential for fine-grained parallel computing on massively parallel computer systems. © 2006 IEEE.

关键词： Dynamic programming

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High-efficient architecture of Godson-T many-core processor 23

High-efficient architecture of Godson-T many-core processor

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23rd IEEE Hot Chips Symposium, HCS 2011

作者： Fan, Dongrui Zhang, Hao Wang, Da Ye, Xiaochun Song, Fenglong Zhang, Junchao Fan, Lingjun Advanced Micro-System Group National Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences China

This article consists of a collection of slides from the author's conference presentation on the special features, system design, processing capabilities, and targeted markets for AMS's Godson-T microprocessor...

ISBN: (纸本)9781467388771

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Protein structure prediction based on a domain clustering database

Protein structure prediction based on a domain clustering da...

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2007 1st International Conference on Bioinformatics and Biomedical Engineering, ICBBE

作者： Ma, Zhaoyun Zhang, Fa Xu, Lin Feng, Shengzhong Liu, Zhiyong Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Institute of Computing Technology Graduate School Chinese Academy of Sciences

ISBN: (纸本)1424411203

Homology modeling, as a successful protein structure prediction method, has two major deficiencies, i.e., the lack of the templates (known structures), and the accuracy of alignment between the query (unknown structure) and its templates. To solve these problems, we have constructed a conservative domain clustering template database, and proposed a profile-based alignment algorithm based on the profile extracted from each domain clustering in the database. The extracted profile can well represent the information of the sequence and structure as well. Compared with other alignment methods, such as T-coffee and Smith-Water man, our results show that with this method it's possible to obtain a higher hit rate for template searching and a more accurate and reliable query-template alignment. Therefore, the quality of protein structure prediction can be improved. © 2007 Crown Copyright.

关键词： Proteins

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Software and hardware co-designed multi-level TLBs for chip multiprocessors

Software and hardware co-designed multi-level TLBs for chip ...

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11th IEEE International Conference on computer and Information technology, CIT 2011 and 11th IEEE International Conference on Scalable computing and Communications, SCALCOM 2011

作者： Zhang, Xiaohui Cong, Ming Chen, Guangqiang Key Laboratory of Computer System and Architecture Institute of Computing Technology Graduate University Beijing China National University of Defense Technology Changsha China

ISBN: (纸本)9780769543888

Translation Lookaside Buffers ( TLBs ) have a significant impact on system performance. Numerous prior studies focus on TLBs design for uniprocessors. With the advent of chip multiprocessors (CMPs), we need a shift to TLBs for chip multiprocessors. This paper presents a software-implemented level-two TLB-SL2-TLB which is a shared level-two TLB for multiprocessors. It not only reduces the cost of TLB refill handler for every processor core, but also reduces the redundant TLB misses' cost for CMPs effectively. Today, CMPs typically employ private per-core TLBs. SL2-TLB together with the hardware TLBs make up a software-hardware co-designed multilevel TLB system which brings great benefit to system performance while avoiding changing the hardware TLB. So it is a convenient and efficient method for CMPs' TLB performance improvement. The benefit brought by SL2-TLB to SPECCPU2000 is less than that to SPECCPU2006, about 5% and 7% separately. Thereinto, the average performance improvement of SPECint 2006 reaches about 12.7%. That is because the overhead for TLB refill is small when the cache is large enough to avoid a miss as walking the page table of applications with small memory footprints. The further optimization for SL2-TLB is kept the SL2-TLB table stay in L2 cache forever by the cache locking scheme. SL2-TLB together with cache locking scheme improves the performances by over 13% for SPECint 2006. And an average performance improvement of over 7% is brought to the new emerging parallel benchmark suite- Princeton Application Repository for Shared-Memory computers (PARSEC). And all the above evaluations are done on Godson-3 processors which is the latest generation of China's most powerful microprocessor family. © 2011 IEEE.

关键词： Benchmarking

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Statistical static timing analysis for circuit aging prediction

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The Journal of China Universities of Posts and Telecommunications 2021年第2期28卷 14-23页

作者： Duan Shengyu Zhai Dongyao Lu Yue Shanghai Engineering Research Center of Intelligent Computing System Shanghai UniversityShanghai 200444China State Key Laboratory of Computer Architecture Institute of Computing TechnologyChinese Academy of SciencesBeijing 100190China School of Electronics and Computer Science University of SouthamptonSouthamptonUK

Complementary metal oxide semiconductor(CMOS)aging mechanisms including bias temperature instability(BTI)pose growing concerns about circuit *** results in threshold voltage increases on CMOS transistors,causing delay shifts and timing violations on logic *** amount of degradation is dependent on the circuit workload,which increases the challenge for accurate BTI aging prediction at the design *** this paper,a BTI prediction method for logic circuits based on statistical static timing analysis(SSTA)is proposed,especially considering the correlation between circuit workload and BTI *** consists of a training phase,to discover the relationship between circuit scale and the required workload samples,and a prediction phase,to present the degradations under different workloads in Gaussian probability *** method can predict the distribution of degradations with negligible errors,and identify 50%more BTI-critical paths in an affordable time,compared with conventional methods.

关键词： bias temperature instability(BTI) reliability prediction statistical static timing analysis(SSTA)

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