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共 517 条记录，以下是81-90 订阅

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M-IVC: Using multiple input vectors to minimize aging-induced delay

M-IVC: Using multiple input vectors to minimize aging-induce...

引用

18th Asian Test Symposium, ATS 2009

作者： Jin, Song Han, Yinhe Zhang, Lei Li, Huawei Li, Xiaowei Yan, Guihai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China

ISBN: (纸本)9780769538648

Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit performance. NBTI degradation has strong dependence on input pattern and duty cycles. Based on this observation, we propose to apply multiple input vectors to the combination circuit in a non-uniform way during standby mode. Multiple input vectors can enhance the capability to control the circuit nodes, achieve smaller duty cycles to reduce the stress time of gates and thus mitigate static NBTI. A constrained multi-object optimization model is formalized to find the optimal combination of duty cycles for timing-critical paths, which in turn minimizes the increase of path delay. An ATPG-like procedure is then presented to generate the corresponding input vectors. Experimental results demonstrate that the delay increase of timing-critical paths can be mitigated significantly under long time NBTI effect (10-year) by only applying a small number of vectors. © 2009 IEEE.

关键词： Negative bias temperature instability

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Diva: A dataflow programming model and its runtime support in java virtual machine

Diva: A dataflow programming model and its runtime support i...

引用

13th IEEE Asia-Pacific computer systems Architecture Conference, ACSAC 2008

作者： Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424426836

Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to program these processors effectively and efficiently, which is known as the "Programming Wall". This paper proposes a systematic approach to attack the problem. We describe an extension of Java programming language with dataflow paradigm and transactional memory. Our approach alleviates the difficulties of parallel programming by providing a higher level of abstraction and relieving programmers of low-level threading and locking details. We also describe the design of a runtime system to support and optimize for the extension. We have implemented a prototype based on Apache Harmony DRL Virtual Machine. Preliminary experimental results on a 16-core SMP machine show that our approach achieves reasonable scalability and can adapt to the variance of available hardware resources. © 2008 IEEE.

关键词： Parallel programming

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Address remapping for static NUCA in noc-based degradable chip-multiprocessors

Address remapping for static NUCA in noc-based degradable ch...

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16th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2010

作者： Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769542898

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme. © 2010 IEEE.

关键词： Network-on-chip

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan

ISBN: (纸本)9781424419227

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead. ©2008 IEEE.

关键词： Multiplexing equipment

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Design of new hash mapping functions

Design of new hash mapping functions

引用

IEEE 9th International Conference on computer and Information technology, CIT 2009

作者： Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769538365

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflictfree. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewedassociative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme. © 2009 IEEE.

关键词： Hash functions

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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique. ©2008 IEEE.

关键词： Chains

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Multi-tiered on-demand resource scheduling for VM-based data center 09

Multi-tiered on-demand resource scheduling for VM-based data...

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2009 9th IEEE/ACM International Symposium on Cluster computing and the Grid, CCGRID 2009

作者： Song, Ying Wang, Hui Yaqiong, Li Feng, Binquan Sun, Yuzhong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769536224

The trend of using virtualization for server consolidation is more and more popular in enterprise data center. However, ondemand resource allocation among the concurrent hosted services in such a virtualized environment is still a challenge. In order to optimize resource allocation among services in data center, this paper proposes a multi-tiered resource scheduling scheme which automatically provides on-demand capacities to the hosted services via resources flowing among VMs. We model the resource flowing using optimization theory. Based on this model, we present a global resource flowing algorithm in the multi-tiered resource scheduling scheme. This algorithm preferentially ensures performance of some critical services by degrading of others to some extent when resource competition arises. Using our RAINBOW prototype, we evaluate the multitiered resource scheduling scheme with the performance improvements for the most critical services up to 9%˜16%, which are 75% of the maximum improvement margin, while performance degradation of others is up to 2%, and leads to 1%˜5% improvements in resource utilization than RAINBOW without resource flowing. Compared with the existent scheme, our work leads to 9% less improvements for critical services, while introduces 39% less degradation to low priority services. © 2009 IEEE.

关键词： Resource allocation

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A microscopic view on community detection in complex networks

A microscopic view on community detection in complex network...

引用

2nd PhD Workshop on Information and Knowledge Management, PIKM'08, Co-located with the 17th ACM Conference on Information and Knowledge Management, CIKM'08

作者： Wang, Yang Song, Huaiming Wang, Weiping An, Mingyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781605583877

The community structure is a basic characteristic of complex networks. A strong community structure has high modularity. It has been proven an NP-Complete problem to identify the community structure with the highest modularity. Many approximate algorithms have been proposed to alleviate the problem. However, they suffer from inefficiency or low quality. In this paper, we propose a two-step method. The first step of our method analyze the vertex similarity of the network, which is a microscopic view. If a pair of vertices are similar enough, they will be put into the same community. The second step of our method focuses on the increment of modularity of the similarity-based communities generated by the first step. If the number of edges between two communities is greater than the expected number based on random choice, the two communities will be merged. The second step is implemented by the CNM algorithm or its improvement CNM+HE'. The similarity-based community remedies the defect on microscope introduced by CNM or CNM+HE'. Our method runs efficiently and finds meaningful communities effectively. We tested the method on more than twenty datasets. The modularity of community structure found by the method is higher than the state-of-the-art algorithm. Copyright 2008 ACM.

关键词： Complex networks

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A low overhead on-chip path delay measurement circuit

A low overhead on-chip path delay measurement circuit

引用

18th Asian Test Symposium, ATS 2009

作者： Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China

ISBN: (纸本)9780769538648

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy. © 2009 IEEE.

关键词： Timing circuits

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Parallelizing a machine translation decoder for multicore computer

Parallelizing a machine translation decoder for multicore co...

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2011 7th International Conference on Natural Computation, ICNC 2011

作者： Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States

ISBN: (纸本)9781424499533

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads. © 2011 IEEE.

关键词： Machine translation

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