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检索条件"机构=Key Laboratory of Computer System and Architeture Institute of Computing Technology"
517 条 记 录,以下是81-90 订阅
排序:
M-IVC: Using multiple input vectors to minimize aging-induced delay
M-IVC: Using multiple input vectors to minimize aging-induce...
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18th Asian Test Symposium, ATS 2009
作者: Jin, Song Han, Yinhe Zhang, Lei Li, Huawei Li, Xiaowei Yan, Guihai Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Chinese Academy of Sciences Graduate University Beijing China
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time and in turn degrading the circuit perf... 详细信息
来源: 评论
Diva: A dataflow programming model and its runtime support in java virtual machine
Diva: A dataflow programming model and its runtime support i...
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13th IEEE Asia-Pacific computer systems Architecture Conference, ACSAC 2008
作者: Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China
Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to progr... 详细信息
来源: 评论
Address remapping for static NUCA in noc-based degradable chip-multiprocessors
Address remapping for static NUCA in noc-based degradable ch...
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16th IEEE Pacific Rim International Symposium on Dependable computing, PRDC 2010
作者: Wang, Ying Zhang, Lei Han, Yinhe Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China
Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability ... 详细信息
来源: 评论
Localized random access scan: Towards low area and routing overhead
Localized random access scan: Towards low area and routing o...
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2008 Asia and South Pacific Design Automation Conference, ASP-DAC
作者: Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan
Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized... 详细信息
来源: 评论
Design of new hash mapping functions
Design of new hash mapping functions
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IEEE 9th International Conference on computer and Information technology, CIT 2009
作者: Song, Fenglong Liu, Zhiyong Fan, Dongrui Zhang, Junchao Yu, Lei Yuan, Nan Lin, Wei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China
Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much confli... 详细信息
来源: 评论
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults
A design- for-diagnosis technique for diagnosing both scan c...
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2008 Asia and South Pacific Design Automation Conference, ASP-DAC
作者: Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China
The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on t... 详细信息
来源: 评论
Multi-tiered on-demand resource scheduling for VM-based data center  09
Multi-tiered on-demand resource scheduling for VM-based data...
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2009 9th IEEE/ACM International Symposium on Cluster computing and the Grid, CCGRID 2009
作者: Song, Ying Wang, Hui Yaqiong, Li Feng, Binquan Sun, Yuzhong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University Chinese Academy of Sciences Beijing China
The trend of using virtualization for server consolidation is more and more popular in enterprise data center. However, ondemand resource allocation among the concurrent hosted services in such a virtualized environme... 详细信息
来源: 评论
A microscopic view on community detection in complex networks
A microscopic view on community detection in complex network...
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2nd PhD Workshop on Information and Knowledge Management, PIKM'08, Co-located with the 17th ACM Conference on Information and Knowledge Management, CIKM'08
作者: Wang, Yang Song, Huaiming Wang, Weiping An, Mingyuan Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China
The community structure is a basic characteristic of complex networks. A strong community structure has high modularity. It has been proven an NP-Complete problem to identify the community structure with the highest m... 详细信息
来源: 评论
A low overhead on-chip path delay measurement circuit
A low overhead on-chip path delay measurement circuit
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18th Asian Test Symposium, ATS 2009
作者: Pei, Songwei Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Academy of Sciences Graduate University of Chinese Beijing 100190 China
In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed... 详细信息
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Parallelizing a machine translation decoder for multicore computer
Parallelizing a machine translation decoder for multicore co...
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2011 7th International Conference on Natural Computation, ICNC 2011
作者: Chen, Long Huo, Wei Mi, Haitao Zhang, Zhaoqing Feng, Xiaobing Li, Zhiyuan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Department of Computer Science Purdue University West Lafayette IN 47907 United States
Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation ... 详细信息
来源: 评论