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检索条件"机构=Key Laboratory of Computer System and architecture"

共 405 条记录，以下是171-180 订阅

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On generation of a universal path candidate set containing testable long paths

On generation of a universal path candidate set containing t...

引用

IEEE International Test Conference

作者： Zijian He Tao Lv Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

We propose an efficient algorithm on generation of a universal path candidate set U that contains testable long paths for delay testing. Some strategies are presented to speed up the depth-first search procedure of U generation, targeting the reduction of checking times of sensitization criteria. Experimental results illustrate that our approach achieves an 8X speedup on average in comparison with the traditional depth-first search approach.

关键词： Automatic test pattern generation

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Gingko: correlating causal paths in distributed systems

Gingko: correlating causal paths in distributed systems

引用

IFIP International Conference on Network and Parallel Computing Workshops (NPC Workshops)

作者： Zhihong Zhang Dan Meng Jianfeng Zhan Lei Wang Yi Jin Yu Wen Hui Wang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Many large-scale systems are distributed systems of multiple communicating components. Finding causal paths of message traces between components throughout these systems is important to uncover runtime behaviors and identify the root cause of failures, but this "art" often hides in the heads of developers or domain experts. Our goal is to design tools and algorithms to help developers record this art into logs and help the modestly-skilled users and system administrators master it to make better use and management of distributed systems. In this paper, we present a methodology that automatically builds the causal paths of message traces by 1) an agreement with programmers on the style and content of logs produced by operational distributed systems they develop and 2) a correlation algorithm to build message causal paths with the clues from these logs. To validate this mechanism, we have implemented Gingko, a prototype providing a tool chain for users to gain better comprehensions of distributed systems and to debug them efficiently when errors happen.

关键词： Runtime Art Clustering algorithms Algorithm design and analysis Programming profession Prototypes Production systems Parallel processing Laboratories computer networks

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Logical clustering for fast clock skew scheduling

Logical clustering for fast clock skew scheduling

引用

Midwest Symposium on Circuits and systems (MWSCAS)

作者： Liang Yang Jiye Zhao Baoxia Fan Ge Zhang Key Laboratory of Computer System and Architecture CAS I. C. T Beijing China

Clock skew scheduling (CSS) is an effective approach to improve the circuit frequency in synchronous circuits. Most previous works about CSS were based on individual registers, but they suffered from scaling problems for large designs. To alleviate this problem, we introduce a novel abstract layer called logical cluster instead of traditional register. A bounded logical clustering method based on timing relation (TRLC) is proposed to reduce the number of independent nodes, and then the tradeoff between aggregation degree and potential upper bound of optimal frequency is analyzed. Furthermore, a bus group logical clustering method (BGLC) is presented to achieve higher aggregation if additional logic information is available. Our experiments show that our approaches achieve significant reduction for the input size of CSS problem even by orders of magnitude, and derive a superlinear or even exponential speedup in runtime.

关键词： Clocks Cascading style sheets Circuits Frequency Registers Clustering methods Timing Upper bound Logic Runtime

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Wear rate leveling: Lifetime enhancement of PRAM with endurance variation 11

Wear rate leveling: Lifetime enhancement of PRAM with endura...

引用

Design Automation Conference

作者： Jianbo Dong Lei Zhang Yinhe Han Ying Wang Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781450306362

The limited write endurance of phase change random access memory (PRAM) is one of the major obstacles for PRAM-based main memory. Wear leveling techniques were proposed to extend its lifetime by balancing writes traffic. Another important concern that need to be considered is endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes will result in lifetime degradation due to the weakest cells. Instead of balancing writes traffic, in this paper we propose wear rate leveling (WRL), a variant of wear leveling, to balance wear rates (i.e., writes traffic/edudrance) of cells across the PRAM chip. After investigating writing behavior of applications and endurance variation, we propose an architecture-level WRL mechanism. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, a novel algorithm, Max Hyper-weight Rematching, is proposed to maximize PRAM lifetime and minimize performance degradation. Experimental results show 19x endurance improvement to prior Wear Leveling.

关键词： Phase change random access memory Writing Programming Degradation Prediction algorithms systematics Complexity theory

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A layered design methodology of cluster system stack

A layered design methodology of cluster system stack

引用

IEEE International Conference on Cluster Computing

作者： Jianfeng Zhan Lei Wang Bibo Tu Zhihong Zhang Yu Wen Yuansheng Chen Wei Zhou Dan Meng Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The application range of cluster has expanded beyond scientific computing, but the present cluster system software fails to provide a flexible architecture to promote code reuse and facilitate building cluster system software for different computing contexts, most of which are developed from scratch case by case, or integrated or packaged with ldquothe best practicerdquo. In this paper, we have proposed a layered design methodology to build cluster system stack with different layers concentrating on different functions, and developed common sets of core service as reusing framework for different computing context. Following this methodology, we have built Phoenix-a complete cluster system stack for both scientific and business computing, which is verified and deployed on Dawning 4000 A super computer for scientific computing and other cluster systems for business computing. The qualitative evaluation and our practices show the design methodology of Phoenix has advantages over other methodologies.

关键词： Design methodology system software Engines computer architecture Software Business Monitoring

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Location Consistency Model Revisited: Problem, Solution and Prospects

Location Consistency Model Revisited: Problem, Solution and ...

引用

IEEE International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT)

作者： Guoping Long Nan Yuan Dongrui Fan Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Location consistency (LC) is a weak memory consistency model which is defined entirely on partial order execution semantics of parallel programs. Compared with sequential consistency (SC), LC is scalable and provides ample theoretical parallelism. This makes LC an interesting memory model in the upcoming many-core parallel processing era. Previous work has pointed out that LC does not guarantee SC execution behavior for all data race free programs. In this paper, we compare the semantics of LC with PRAM consistency and memory coherence, and prove that LC is strictly weaker than PRAM consistency. For data race free programs, we prove that the semantics of LC is equivalent to memory coherence. In addition, by introducing memory ordering semantics into LC judiciously, we prove that the enhanced model is equivalent to SC for data race free programs. Finally, we discuss possible solutions for adding reasoning rules for LC-like weak memory models.

关键词： Coherence Phase change random access memory Distributed computing Parallel processing Programming profession Application software Laboratories Concurrent computing computer architecture Counting circuits

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An Innovative Power-Efficient architecture for Input Buffer of Network on Chip

An Innovative Power-Efficient Architecture for Input Buffer ...

引用

IEEE International Conference on Integration Technology (ICIT)

作者： Kun Huang Jun Wang Ge Zhang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

In recent years, the power efficiency of NoC (network on chip) is becoming a new research direction. For tiled CMP (single-chip multi processor), the characteristics of transmission data of NoC in a tiled CMP should be noticed that the probability of which the transmitted bits are zero is much bigger than that of which the bits are one. This paper proposes an innovative power-efficient architecture of input buffer of NoC, which makes use of the mentioned characteristics, can improve the power efficiency of the NoC of tiled CMP significantly.

关键词： Network-on-a-chip Energy consumption computer architecture Microprocessors Delay system-on-a-chip Buffer storage Routing Laboratories computer networks

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A Parallel Algorithm for Computing Betweenness Centrality

A Parallel Algorithm for Computing Betweenness Centrality

引用

International Conference on Parallel Processing (ICPP)

作者： Guangming Tan Dengbiao Tu Ninghui Sun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

In this paper we present a multi-grained parallel algorithm for computing betweenness centrality, which is extensively used in large-scale network analysis. Our method is based on a novel algorithmic handling of access conflicts for a CREW PRAM algorithm. We propose a proper data-processor mapping, a novel edge-numbering strategy and a new triple array data structure recording the shortest path for eliminating conflicts to access the shared memory. The algorithm requires O(n+m) space and O((nm)/p) ( or O((nm+n 2 logn)/p)) time for unweighted (or weighted) graphs, and it is a work-optimal CREW PRAM algorithm. On current multi-core platforms, our algorithm outperforms the previous algorithm by 2-3 times.

关键词： Parallel algorithms Concurrent computing Proteins Phase change random access memory Complex networks Algorithm design and analysis Large-scale systems Parallel processing Fungi computer networks

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An interconnect-aware power efficient cache coherence protocol for CMPs

An interconnect-aware power efficient cache coherence protoc...

引用

International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Hongbo Zeng Jun Wang Ge Zhang Weiwu Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The continuing shrinking of technology enables more and more processor cores to reside on a single chip. However, the power consumption and delay of global wires have presented a great challenge in designing future chip multiprocessors. With these overheads of wires properly accounted for, researchers have explored some efficient on- chip network designs in the domain of larger scale caches. While in the paper, we attempt to reduce the interconnect power consumption with a novel cache coherence protocol. Conventional coherence protocols are kept independent from underlying networks for flexibility reasons. But in CMPs, processor cores and the on-chip network are tightly integrated. Exposing features of interconnect networks to protocols will unveil some optimization opportunities for power reduction. Specifically, by utilizing the location information of cores on a chip, the coherence protocol we propose in this work chooses to response the requester with the data copy in the closest sharer of the desired cache line, other than fetching it from distant L2 cache banks. This mechanism reduces the hops cache lines must travel and eliminates the power that would have incurred on the corresponding not-traveled links. To get accurate and detailed power information of interconnects, we extract wire power parameters by physical level simulation (HSPICE) and obtain router power by synthesizing RTL with actual ASIC libraries. We conduct experiments on a 16-core CMP simulator with a group of SPLASH2 benchmarks. The results demonstrate that an average of 16.3% L2 cache accesses could be optimized, resulting in an average 9.3% power reduction of data links with 19.2% as the most. This mechanism also yields a performance speedup of 1.4%.

关键词： Protocols Energy consumption Wires Network-on-a-chip Power system interconnection Delay Large-scale systems Switches Acceleration Laboratories

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Using Index in the MapReduce Framework

Using Index in the MapReduce Framework

引用

International Asia-Pacific Web Conference (APWEB)

作者： Mingyuan An Yang Wang Weiping Wang Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

MapReduce is a programming framework introduced by Google for large-scale data processing. It is usually used in a scan-centric fashion where all the data are split into blocks and Maps are generated for each block to scan and process the data in the block, then Reduces merge outputs from all the Maps. When a query intends to process only a subset of the data selected by a predicate, this brute-force method may cause extra I/O overhead spent on irrelevant data, and the overhead for initiating so many Maps may be non-trivial given that the actually interesting data for the query is comparatively small in volume. We propose an approach to integrate the index into the MapReduce execution in which only an appropriate number of Maps are generated, each of which accesses the data using an index. This approach incurs random I/O and remote access to data, so the overall performance depends on both system parameters and the query characteristics. We build a cost model for both this index access execution and the traditional full scan execution. This cost model can be used to choose between the two execution modes before executing a query. Experiments show that the index access execution can greatly outperform full scan execution when the selectivity of the predicate is low, and the cost model predicts the actual execution cost very well so can be used to determine the execution plan for a query.

关键词： Flash memory Indexing computer science Delay Tree data structures Energy efficiency Nonvolatile memory Costs Mechanical factors Energy storage

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