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Parallelizing a Machine Translation Decoder for Multicore computer

Parallelizing a Machine Translation Decoder for Multicore Co...

引用

2011 Seventh International Conference on Natural Computation(第七届自然计算国际会议 ICNC 2011)

作者： Zhaoqing Zhang Haitao Mi Long Chen Xiaobing Feng Wei Huo Zhiyuan Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academ Department of Computer Science Purdue University West Lafayette US IN 47907

Machine translation (MT), with its broad potential use, has gained increased attention from both researchers and software vendors. To generate high quality translations, however, MT decoders can be highly computation intensive. With significant raw computing power, multi-core microprocessors have the potential to speed up MT software on desktop machines. However, retrofitting existing MT decoders is a nontrivial issue. Race conditions and atomicity issues are among those complications making parallelization difficult. In this article, we show that, to parallelize a state-of-the-art MT decoder, it is much easier to overcome such difficulties by using a process-based parallelization method, called functional task parallelism, than using conventional thread-based methods. We achieve a 7.60 times speed up on an 8-core desktop machine while making significantly less changes to the original sequential code than required by using multiple threads.

关键词： Decoding Instruction sets Load modeling Computational modeling Memory management Sorting

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Performance and Power Efficiency Analysis of the Symmetric Cryptograph on Two Stream Processor architectures

Performance and Power Efficiency Analysis of the Symmetric C...

引用

International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP)

作者： Guang Xu Hong An Gu Liu Ping Yao Mu Xu Wenting Han Xiaoqiang Li Xiurui Hao Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Multimedia and some scientific applications have achieved good performance on the stream processor architecture by employing the stream programming model. In order to find out the way to accelerate the symmetric cryptograph on stream processor, we implement and analyze cryptograph algorithms on different stream processors in this paper. Four cipher algorithms including RC5, AES, TWOFISH and 3DES in ECB model are implemented on three platforms, which are stream processor SPI Storm SP16-G160, NVIDIA GeForce 9800GTX, Intel Core2 dual-core processor E7300. The difference of architecture between two stream processors and the character of programming model are described. When we compare throughput rate of these applications, 9800GTX is shown with 4-30x performance improvement over E7300, SP16 achieves the highest power efficiency and obtains 15-20x increase over E7300 in Gops/Watt.

关键词： Performance analysis Cryptography Streaming media computer architecture Acceleration Signal processing algorithms Storms Multimedia systems High performance computing Hardware

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Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors 10

Performance-asymmetry-aware topology virtualization for defe...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Lei Zhang Yue Yu Jianbo Dong Yinhe Han Shangping Ren Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China Department of Computer Science Illinois Institute of Technology USA

ISBN: (纸本)9783981080162

Topology virtualization techniques are proposed for NoC-based many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior work focuses on homogeneous cores with symmetric performance and optimizes on-chip communication only. However, core-to-core performance asymmetry due to manufacturing process variations poses new challenges for constructing virtual topologies. Lower performance cores may scatter over a virtual topology, while operating systems typically allocate tasks to continuous cores. As a result, parallel applications are probably assigned to a region containing many slower cores that become bottlenecks. To tackle the above problem, in this paper we present a novel performance-asymmetry-aware reconfiguration algorithm Bubble-Up based on a new metric called core fragmentation factor (CFF). Bubble-Up can arrange cores with similar performance closer, yet maintaining reasonable hop distances between virtual neighbors, thus accelerating applications with higher degree of parallelism, without changing existing allocation strategies for OS. Experimental results show its effectiveness.

关键词： Network topology Network-on-a-chip Programming profession Hardware system-on-a-chip Manufacturing processes Scattering Operating systems Parallel processing Throughput

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Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant system

Reliability Optimization of Reconfigurable Computing-Based F...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Mi Zhou Lihong Shang Yu Hu School of Computer Science and Engineering Beihang University Beijing China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfiguration computing based fault tolerant system which is self-repairable in case of failure, and is solved as a nonlinear planning problem. The assumptions made in previous work are relaxed. An improved algorithm is proposed to reduce the time cost for calculating the reliability. Experiments on ITCpsila99 benchmark circuits are carried out. Results show the proposed approach outperforms previous works in failure rate with less memory cost to store configurations.

关键词： Fault tolerant systems Field programmable gate arrays Circuit faults Tiles High performance computing Redundancy Costs Logic devices Reconfigurable logic Runtime

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A Priority-Aware NoC to Reduce Squashes in Thread Level Speculation for Chip Multiprocessors

A Priority-Aware NoC to Reduce Squashes in Thread Level Spec...

引用

International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Wenbo Dai Hong An Qi Li Gongming Li Bobin Deng Shilei Wu Xiaomei Li Yu Liu School of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Thread Level Speculation (TLS) is a technique aims at boosting the performance of sequential programs running on Chip Multiprocessors (CMPs) by automatically parallelizing them. It exempts programmers from the heavy task of parallel programming. But its performance may suffer from frequent squashing caused by inter-thread data dependency violation. In this paper, we propose a Network-on-Chip (NoC) in CMP that employs a priority-aware packet arbitration policy. Packet scheduling guided by such policy reduces the occurrence of TLS squashes. Simulation results with 5 applications show that our policy reduces squashes by 22% in best case and 15% on average. Moreover, our priority aware approach could be generalized to similar scenarios in which different threads running on CMP manifest different priorities.

关键词： Instruction sets Nickel Art Switches Scalability Protocols

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Investigation of Factors Impacting Thread-Level Parallelism from Desktop, Multimedia and HPC Applications

Investigation of Factors Impacting Thread-Level Parallelism ...

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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)

作者： Yaobin Wang Hong An Jie Yan Qi Li Wenting Han Li Wang Gu Liu Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Applications of different categories contain varying levels of data, instruction and thread-level parallelism inherently. It's important to explore the potential coarse-grain thread-level parallelism in different applications to guide the computing resources allocation problem in multicore chips. Up to now, lots of depth researches have been mainly concentrated in the desktop applications. In order to fully understand thread level parallel (TLP) technology's applicability, this paper proposes a criterion for selecting the region to be executed in parallel and analyzes applications' performance impacting factors (computation, coverage parallelism, thread size, inter-thread control dependence feature and inter-thread data dependence feature) by our dynamic profiling tool set. It explores the TLP potentials in desktop, multimedia and high performance computing (HPC) fields by demonstrating different speedup potentials that can be exploited using different core numbers. The experimental results show that the majority of desktop applications can only make an effective use of 2 cores' computing resources while most multimedia and HPC applications can use 8-16 cores' computing resources efficiently in the coarse-grain thread-level parallelism. Although TLP technology didn't perform well in the desktop applications that have serious data dependence problem, it's suitable for most multimedia and HPC applications that have large calculation, moderate thread size, and fuzzy dependence but easy to resolve.

关键词： Parallel processing Yarn Concurrent computing Multicore processing computer science Application software computer architecture Resource management Performance analysis Multimedia computing

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Improving data availability for a cluster file system through replication

Improving data availability for a cluster file system throug...

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International Symposium on Parallel and Distributed Processing (IPDPS)

作者： Jin Xiong Jianyu Li Rongfeng Tang Yiming Hu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Department of Electrical & Computer Engineering and Computer Science University of Cincinnati USA

Data availability is a challenging issue for large- scale cluster file systems built upon thousands of individual storage devices. Replication is a well-known solution used to improve data availability. However, how to efficiently guarantee replicas consistency under concurrent conflict mutations remains a challenge. Moreover, how to quickly recover replica consistency from a storage server crash or storage device failure is also a tough problem. In this paper, we present a replication-based data availability mechanism designed for a large-scale cluster file system prototype named LionFS. Unlike other replicated storage systems that serialize replica updates, LionFS introduces a relaxed consistency model to enable concurrent updating all replicas for a mutation operation, greatly reducing the latency of operations. LionFS ensures replica consistency if applications use file locks to synchronize the concurrent conflict mutations. Another novelty of this mechanism is its light-weight log, which only records failed mutations and imposes no overhead on failure-free execution and low overhead when some storage devices are unavailable. Furthermore, recovery of replica consistency needs not stop the file system services and running applications. Performance evaluation shows that our solution achieves 50-70% higher write performance than serial replica updates. The logging overhead is shown to be low, and the recovery time is proportional to the amount of data written during the failure.

关键词： File systems Genetic mutations computer crashes Large-scale systems Availability Peer to peer computing Delay Bandwidth Laboratories computer architecture

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A Non-blocking Programming Framework for Pipeline Application on Multi-core Platform

A Non-blocking Programming Framework for Pipeline Applicatio...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Xiaoqiang Li Hong An Gu Liu Wenting Han Mu Xu Wei Zhou Qi Li School of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Many applications meet certain programming patterns like pipeline, fork-join, do-all etc. While tools such as OS threads and OpenMP allow programmers only to express task or data parallelism, special support for programming patterns is distinctly lacking. Intel threading building blocks (TBB) is developed to address this problem, but its scheduler is general and not optimized for any of its parallel algorithms which include pipeline specially. In this paper, we provide a non-blocking framework for pipeline application on multi-core platform. We target linear pipeline in which each filter has one entrance and one exit. We design a novel work-stealing scheduler optimized specially for pipeline application: first, priority based stealing, priority is calculated for each filter in pipeline so that a worker can find the optimal "victim" easily when it needs to steal, second, multiple tasks can be stolen at a time so that much stealing time is reduced. A non-block queue is used to store intermediate result to reduce lock overhead and increase scalability. We apply our framework to four case studies, including text filter, two fish, ferret, ded up. And our framework reduces execution time of TBB by 72% in best case and 20% on average on an 8 core machine.

关键词： Pipelines Optimization Programming Load management Parallel processing Arrays

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BTMD: A Framework of Binary Translation Based Malcode Detector

BTMD: A Framework of Binary Translation Based Malcode Detect...

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International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, CyberC

作者： Zheng Shan Haoran Guo Jianmin Pang Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China National Digital Switching System Engineering & Technology Research Center Zhengzhou China

Binary Translation technology is used to convert binary code of one Instruction Set architecture (ISA) into another. This technology can solve the software-inheritance problem and ISA-compatibility between different computers architecture. In this paper, we describe BTMD (Binary Translation based Malcode Detector), a novel framework that exploits static and dynamic binary translation features to detect broad spectrum malware and prevent its execution. By operating directly on binary code with MD Rules on the availability of source code, BTMD is appropriate for translating low-level binary code to high-level proper representation, obtaining CFG (Control Flow Graph) and other high-level Control Structure by MD Parser. Then Critical API Graph based on CFG is generated to do sub graph matching with the defined Malware Behavior Template. MD Engine in BTMD is called to undertake the process to take on the remaining code analysis. Compared with other detection approaches, BTMD is found to be very efficient in terms of detection capability and false alarm rate.

关键词： Binary codes Engines computers Decoding Detectors computer architecture Malware

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OpenPro: A Dynamic Profiling Tool Set for Exploring Thread-Level Speculation Parallelism

OpenPro: A Dynamic Profiling Tool Set for Exploring Thread-L...

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International Conference on computer and Electrical Engineering, ICCEE

作者： Yaobin Wang Hong An Bo Liang Li Wang Rui Guo Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Thread-level speculative (TLS) execution can facilitate automatic parallelization of programs that exhibit complicated memory access patterns, which make complete compile-time dependence analysis either impossible or extremely complicated. The decision on where to speculate can make a large difference in the resulting performance. Up to now, we still lack of appropriate dynamic profiling tool used to find and effectively exploit TLS parallelism. In this paper, we proposed a criterion for selecting the region to be speculatively executed and introduce a dynamic profiling tool set "OpenPro" which can be used to explore TLS parallelism for various applications in depth. The OpenPro can be used to analyze the key factors on TLS parallelism, such as inter-thread data dependence, inter-thread control-flow misprediction and inter-thread load imbalance, and to show the potential speedup to evaluate whether a given application or parts of it are suitable for TLS technology. By profiling the SPEC CPU2000 integer benchmark suite, we found that the TLS technology is not suitable for the traditional desktop applications.

关键词： Parallel processing Yarn Concurrent computing Runtime computer science Laboratories computer architecture Pattern analysis Delay Data analysis

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