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IEEE International Conference on Networking, architecture and Storage

作者： Cai, Songsong Yang, Yongqiang Lin, Chuanwen Liu, Qi Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate University of Chinese Academy of Sciences Beijing China Dept. of Computer Science and Technology University of Science and Technology of China Hefei China Loongson Technology Corporation Limited Beijing China

ISBN: (纸本)9780769545097

In Java programs, it needs to use the information of the method type to resolve the virtual method dynamically, which restricts the performance greatly. Currently, the solution is mainly the technique of inline caching, which can be divided into two categories: monomorphic inline caching and polymorphic inline caching. Because of the simple implementation of monomorphic inline caching, it is more commonly used, but it cannot resolve the problem of frequently seeing different types of objects at one call site. Although polymorphic inline caching can solve this problem, it is costly. This paper presents the CAM hardware table, proposes a virtual method invoking mechanism based on software and hardware co-design. It solves the problem of frequently seeing different types of objects at one call site, and does not introduce additional overhead. The experimental evaluation shows that it improves the cached hit rate from 13.3% to 76.4% and improves 16.2% performance of the virtual test;it improves the performance of SPECjvm98 by 6.4% on average. © 2011 IEEE.

关键词： Virtual reality

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Optimizing MPI Alltoall communications in multicore clusters

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2013年第8期50卷 1744-1754页

作者： Li, Qiang Sun, Ninghui Huo, Zhigang Ma, Jie High Performance Computer Research Center Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100190 China University of Chinese Academy of Sciences Beijing 100039 China

MPI Alltoall is an important collective operation. In multicore clusters, many processes run in a node. On the one hand, shared memory can be adopted to optimize Alltoall communications of small messages by leader-based schemes. However, as these schemes adopt a fixed number of leader processes, the optimal performance can't be obtained for all small messages. On the other hand, processes within a node contend for the same network resource. In Alltoall communications of large messages, many synchronization messages are used. Nevertheless, the contention makes their latency increase many times and the synchronization overhead can't be ingored. To solve these problems, two optimizations are presented. For small messages, the PLP method adopts changeable numbers of leader processes. For large messages, the LSS method reduces the number of synchronization messages from 3N to 2√N. The evaluations prove two methods. For small messages, the PLP method always obtains optimal performance. For large messages, the LSS method brings almost constant improvement percentage. The performance is improved by 25% for 32 KB and 64 KB messages.

关键词： Synchronization

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nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications

nGFSIM : A GPU-based fault simulator for 1-to-n detection an...

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IEEE International Test Conference

作者： Huawei Li Dawen Xu Yinhe Han Kwang-Ting Cheng Xiaowei Li Department of Electrical and Computer Engineering University of California Santa Barbara USA Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

We present nGFSIM, a GPU-based fault simulator for stuck-at faults which can report the fault coverage of one-to n-detection for any specified integer n using only a single run of fault simulation. nGFSIM, which explores the massive parallelism in the GPU architecture and optimizes the memory access and usage, enables accelerated fault simulation without the need of fault dropping. We show that nGFSIM offers a 25X speedup in comparison with a commercial tool and enables new applications in test selection.

关键词： Circuit faults Graphics processing unit Integrated circuit modeling Instruction sets Logic gates Computational modeling Kernel

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Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs 10

Accelerating Lightpath setup via broadcasting in binary-tree...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In this paper, we propose a binary-tree waveguide connected Optical-Network-on-Chip (ONoC) to accelerate the establishment of the lightpath. By broadcasting the control data in the proposed power-efficient binary-tree waveguide, the maximal hops for establishing lightpath is reduced to two. With extensive simulations and analysis, we demonstrate that the proposed ONoC significantly reduces the setup time, and then the packet latency.

关键词： Optical waveguides Acceleration Broadcasting Network-on-a-chip Optical interconnections Delay Optical modulation Logic Microcavities Optical devices

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Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

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Pacific Rim International Symposium on Dependable Computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

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Adaptive Diagnostic Pattern Generation for Scan Chains

Adaptive Diagnostic Pattern Generation for Scan Chains

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Fei Wang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, a SAT-based technique is proposed to adaptively generate patterns to diagnose stuck-at faults in scan chains. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can dramatically reduce the number of diagnostic patterns while obtain high diagnosis resolution.

关键词： Circuit faults Electronic equipment testing system testing Application software Circuit testing Signal resolution Failure analysis Automatic test pattern generation Frequency Test pattern generators

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A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEWORK FOR MOBILE TERMINALS

A CROSS-PLATFORM CONTEXT-AWARE APPLICATION DEVELOPING FRAMEW...

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2012 IEEE 2nd International Conference on Cloud Computing and Intelligence systems

作者： Pingyi Wang Jingling Zhao Qing Liao School of Computer Science Beijing University of Posts and Telecommunications Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications

The increasing number of mobile terminals facilitates the development of context-aware applications. However, developing a context aware application is still a complex work, which involves mechanisms of context acquisition and context processing. In order to release the developer’s burden, many context aware frameworks emerged. But none of them yet has sufficient consideration of mobile environment characteristics. Besides, restricted to the mobile platform, the developed application could not achieve cross-platform deployment. A cross-platform context-aware application developing framework for mobile terminals is proposed in this paper. This framework could shield system differences, centralize context acquisition, context modeling, context storing, context interpretation and context aggregation for many context aware applications on the same terminal. Applying the framework, data of same sensor would not be duplicated processed by many context aware applications. Context aware application would be built faster. And mobile terminal resources would be used more efficiently.

关键词： Context-awareness Cross-platform Mobile terminal Framework

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PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse of Optimizations on GPGPUs

PADS: A Pattern-Driven Stencil Compiler-Based Tool for Reuse...

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International Conference on Parallel and Distributed systems (ICPADS)

作者： Dongni Han Shixiong Xu Li Chen Lei Huang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China Computer Science Department Prairie View A&M University USA

Stencil computations are core of wide range of scientific and engineering applications. A lot of efforts have been put into improving efficiency of stencil calculations on different platforms, but unfortunately it is not easy to reuse. In this paper we present a PAttern-Driven Stencil compiler-based tool and a simple tuning system to reuse those well optimized methods and codes. We also suggest extensions to OpenMP, depicting high-level data structures in order to facilitate recognition of various stencil computation patterns. The PADS allows programmers to rewrite kernel of stencils or reuse source-to-source translator outputs as optimized stencil template codes with related tuning parameters, In addition, PADS consists of a OpenMP to CUDA translator and code generator using optimized template codes. It also obtains architecture-specific parameters to tune stencils across different GPU platforms. To demonstrate our system flexibility and performance portability, we illustrate four different stencil computations, Laplacian operator with Jacobi iterative method, divergence operator, 3 dimension 25 point stencil and a 2D heat equation using ADI method with periodic boundary conditions. PADS succeeds in generating all these four stencil codes using different optimization strategies and delivers a promising performance improvement.

关键词： Pattern matching Kernel Tuning Libraries Optimization Generators

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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

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Pacific Rim International Symposium on Dependable Computing

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance system recovery computer networks Region 4 Shape Laboratories computer architecture

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An abstraction-guided simulation approach using Markov models for microprocessor verification 10

An abstraction-guided simulation approach using Markov model...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Tao Zhang Tao Lv Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

In order to combine the power of simulation-based and formal techniques, semi-formal methods have been widely explored. Among these methods, abstraction-guided simulation is a quite promising one. In this paper, we propose an abstraction-guided simulation approach aiming to cover hard-to-reach states in functional verification of microprocessors. A Markov model is constructed utilizing the high level functional specification, i.e. ISA. Such model integrates vector correlations. Furthermore, several strategies utilizing abstraction information are proposed as an effective guidance to the test generation. Experimental results on two complex microprocessors show that our approach is more efficient in covering hard-to-reach states than similar methods. Comparing with some work with other intelligent engines, our approach could guarantee higher hit ratio of target states without efficiency loss.

关键词： Microprocessors Testing Computational modeling Engines Data mining computer simulation Power system modeling Laboratories computer architecture Instruction sets

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