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检索条件"机构=Key Laboratory of Computer System and architecture"
405 条 记 录,以下是251-260 订阅
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Localizing Loads Execution in a Data Cache Distributed Processor architecture
Localizing Loads Execution in a Data Cache Distributed Proce...
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International Association of computer Science and Information Technology - Spring Conference, IACSITSC
作者: Ruiling Dou Hong An Rui Guo Wenting Han Ming Cong Yongqing Ren Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China
To scale with the on-chip wire delay, the inside of a processor will further be partitioned into more small banks. As the amount of data cache bank scales, the load routing latency will contribute a considerable porti... 详细信息
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A Program Behavior Study of Block Cryptography Algorithms on GPGPU
A Program Behavior Study of Block Cryptography Algorithms on...
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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)
作者: Gu Liu Hong An Wenting Han Guang Xu Ping Yao Mu Xu Xiurui Hao Yaobin Wang Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China
Recently many studies have been made to map cryptography algorithms onto graphics processors (GPU), and gained great performances. This paper does not focus on the performance of a specific program exploited by using ... 详细信息
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Performance and Power Efficiency Analysis of the Symmetric Cryptograph on Two Stream Processor architectures
Performance and Power Efficiency Analysis of the Symmetric C...
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International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP)
作者: Guang Xu Hong An Gu Liu Ping Yao Mu Xu Wenting Han Xiaoqiang Li Xiurui Hao Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China
Multimedia and some scientific applications have achieved good performance on the stream processor architecture by employing the stream programming model. In order to find out the way to accelerate the symmetric crypt... 详细信息
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Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant system
Reliability Optimization of Reconfigurable Computing-Based F...
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IEEE International Conference on High Performance Computing and Communications (HPCC)
作者: Mi Zhou Lihong Shang Yu Hu School of Computer Science and Engineering Beihang University Beijing China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China
Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfiguration computing based fault tolerant sys... 详细信息
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Investigation of Factors Impacting Thread-Level Parallelism from Desktop, Multimedia and HPC Applications
Investigation of Factors Impacting Thread-Level Parallelism ...
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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)
作者: Yaobin Wang Hong An Jie Yan Qi Li Wenting Han Li Wang Gu Liu Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China
Applications of different categories contain varying levels of data, instruction and thread-level parallelism inherently. It's important to explore the potential coarse-grain thread-level parallelism in different ... 详细信息
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Small Delay Fault Simulation for Sequential Circuits
Small Delay Fault Simulation for Sequential Circuits
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Pacific Rim International Symposium on Dependable Computing
作者: Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is present... 详细信息
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A Low Overhead On-Chip Path Delay Measurement Circuit
A Low Overhead On-Chip Path Delay Measurement Circuit
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Asian Test Symposium (ATS)
作者: Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China
In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed... 详细信息
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Impact of Hazards on Pattern Selection for Small Delay Defects
Impact of Hazards on Pattern Selection for Small Delay Defec...
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Pacific Rim International Symposium on Dependable Computing
作者: Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test p... 详细信息
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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes
A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...
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Pacific Rim International Symposium on Dependable Computing
作者: Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty route... 详细信息
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A Scalable Scan architecture for Godson-3 Multicore Microprocessor
A Scalable Scan Architecture for Godson-3 Multicore Micropro...
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Asian Test Symposium (ATS)
作者: Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China
This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-... 详细信息
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