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Localizing Loads Execution in a Data Cache Distributed Processor architecture

Localizing Loads Execution in a Data Cache Distributed Proce...

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International Association of computer Science and Information Technology - Spring Conference, IACSITSC

作者： Ruiling Dou Hong An Rui Guo Wenting Han Ming Cong Yongqing Ren Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

To scale with the on-chip wire delay, the inside of a processor will further be partitioned into more small banks. As the amount of data cache bank scales, the load routing latency will contribute a considerable portion to program executing time. In a tiled processor like T-Flex, we observed that the average load routing latency (hit in data cache) can be largely reduced (by 72.1%) when data is perfectly placed in where the load issues. To reduce the long routing latency of critical loads, we give out a solution for localizing load execution at issuing side in this paper. However, this method will induce overhead of data copies and extra communications to maintain coherence and memory order. We explore the design space for localizing data access, with special respect to maximizing benefits at expense of relatively small overhead. We observed the access frequency and load store behaviors for different copies vary largely, with large amount of successive load accesses concentrating on small amount of data blocks. Our experiments show that with special replication and data copy invalidation strategies, copying overhead will be controlled while maintaining considerable performance profits.

关键词： Delay Tiles computer architecture Routing Processor scheduling computer science Springs Wire Space exploration Art

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A Program Behavior Study of Block Cryptography Algorithms on GPGPU

A Program Behavior Study of Block Cryptography Algorithms on...

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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)

作者： Gu Liu Hong An Wenting Han Guang Xu Ping Yao Mu Xu Xiurui Hao Yaobin Wang Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Recently many studies have been made to map cryptography algorithms onto graphics processors (GPU), and gained great performances. This paper does not focus on the performance of a specific program exploited by using all kinds of optimization methods algorithmically, but the intrinsic reason which lies in GPU architectural features for this performance improvement. Thus we present a study of several block encryption algorithms(AES, TRI-DES, RC5, TWOFISH and the chained block cipher formed by their combinations) processing on GPU using CUDA. We introduce our CUDA implementations, and investigate the program behavioral characteristics and their impacts on the performance in four aspects. We find that the number of threads used by a CUDA program can affect the overall performance fundamentally. Many block encryption algorithms can benefit from the shared memory if the capacity is large enough to hold the lookup tables. The data stored in device memory should be organized purposely to avoid performance degradation. Besides, the communication between host and device may turn out to be the bottleneck of a program. Through these analyses we hope to find out an effective way to optimize a CUDA program, as well as to reveal some desirable architectural features to support block encryption applications better.

关键词： Cryptography computer architecture Acceleration Runtime computer science Parallel processing Hardware Laboratories computer graphics Optimization methods

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Performance and Power Efficiency Analysis of the Symmetric Cryptograph on Two Stream Processor architectures

Performance and Power Efficiency Analysis of the Symmetric C...

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International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP)

作者： Guang Xu Hong An Gu Liu Ping Yao Mu Xu Wenting Han Xiaoqiang Li Xiurui Hao Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Multimedia and some scientific applications have achieved good performance on the stream processor architecture by employing the stream programming model. In order to find out the way to accelerate the symmetric cryptograph on stream processor, we implement and analyze cryptograph algorithms on different stream processors in this paper. Four cipher algorithms including RC5, AES, TWOFISH and 3DES in ECB model are implemented on three platforms, which are stream processor SPI Storm SP16-G160, NVIDIA GeForce 9800GTX, Intel Core2 dual-core processor E7300. The difference of architecture between two stream processors and the character of programming model are described. When we compare throughput rate of these applications, 9800GTX is shown with 4-30x performance improvement over E7300, SP16 achieves the highest power efficiency and obtains 15-20x increase over E7300 in Gops/Watt.

关键词： Performance analysis Cryptography Streaming media computer architecture Acceleration Signal processing algorithms Storms Multimedia systems High performance computing Hardware

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Reliability Optimization of Reconfigurable Computing-Based Fault-Tolerant system

Reliability Optimization of Reconfigurable Computing-Based F...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Mi Zhou Lihong Shang Yu Hu School of Computer Science and Engineering Beihang University Beijing China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

Domain-partition (DP) model is a general model for reliability maximization problem under given redundancy. In this paper, an improved DP model is used to formulate a reconfiguration computing based fault tolerant system which is self-repairable in case of failure, and is solved as a nonlinear planning problem. The assumptions made in previous work are relaxed. An improved algorithm is proposed to reduce the time cost for calculating the reliability. Experiments on ITCpsila99 benchmark circuits are carried out. Results show the proposed approach outperforms previous works in failure rate with less memory cost to store configurations.

关键词： Fault tolerant systems Field programmable gate arrays Circuit faults Tiles High performance computing Redundancy Costs Logic devices Reconfigurable logic Runtime

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Investigation of Factors Impacting Thread-Level Parallelism from Desktop, Multimedia and HPC Applications

Investigation of Factors Impacting Thread-Level Parallelism ...

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Japan-China Joint Workshop on Frontier of computer Science and Technology (FCST)

作者： Yaobin Wang Hong An Jie Yan Qi Li Wenting Han Li Wang Gu Liu Department of Computer Science and Technology University of Science and Technology Hefei China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Applications of different categories contain varying levels of data, instruction and thread-level parallelism inherently. It's important to explore the potential coarse-grain thread-level parallelism in different applications to guide the computing resources allocation problem in multicore chips. Up to now, lots of depth researches have been mainly concentrated in the desktop applications. In order to fully understand thread level parallel (TLP) technology's applicability, this paper proposes a criterion for selecting the region to be executed in parallel and analyzes applications' performance impacting factors (computation, coverage parallelism, thread size, inter-thread control dependence feature and inter-thread data dependence feature) by our dynamic profiling tool set. It explores the TLP potentials in desktop, multimedia and high performance computing (HPC) fields by demonstrating different speedup potentials that can be exploited using different core numbers. The experimental results show that the majority of desktop applications can only make an effective use of 2 cores' computing resources while most multimedia and HPC applications can use 8-16 cores' computing resources efficiently in the coarse-grain thread-level parallelism. Although TLP technology didn't perform well in the desktop applications that have serious data dependence problem, it's suitable for most multimedia and HPC applications that have large calculation, moderate thread size, and fuzzy dependence but easy to resolve.

关键词： Parallel processing Yarn Concurrent computing Multicore processing computer science Application software computer architecture Resource management Performance analysis Multimedia computing

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Small Delay Fault Simulation for Sequential Circuits

Small Delay Fault Simulation for Sequential Circuits

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Pacific Rim International Symposium on Dependable Computing

作者： Li Liu Jishun Kuang Huawei Li School of Computer and Communication Hunan University Changsha China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Small-delay faults may escape detection by transition fault patterns, but traditional transition fault simulator can not detect this phenomenon. A fault simulator detecting test escape of small-delay faults is presented. The sizes of the faults are less than one system clock cycle. For our method, the delay distribution in the CUT is considered, and the fault size is quantized as times of the propagation delay in an inverter. By a waveform simulation based on Boolean process, the simulator is able to show the time interval that the fault affects and determine whether the propagation delay exceeds the system clock cycle. It might give ATPG a little of useful information.

关键词： Circuit faults Circuit simulation Sequential circuits Electrical fault detection Fault detection Propagation delay Clocks Circuit testing Inverters Automatic test pattern generation

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A Low Overhead On-Chip Path Delay Measurement Circuit

A Low Overhead On-Chip Path Delay Measurement Circuit

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Asian Test Symposium (ATS)

作者： Songwei Pei Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.

关键词： Integrated circuit measurements Delay effects Area measurement Time measurement Delay lines Electrical fault detection Fault detection Debugging Circuit faults Added delay

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Impact of Hazards on Pattern Selection for Small Delay Defects

Impact of Hazards on Pattern Selection for Small Delay Defec...

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Pacific Rim International Symposium on Dependable Computing

作者： Jie Wang Huawei Li Yinghua Min Xiaowei Li Huaguo Liang School of Computer and Information Hefei University of Technology Hefei China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Hazards ubiquitously exist in combinational circuits, and then should be taken into account for delay testing. This paper analyzes the impact of hazards on small-delay defect (SDD) detection, and presents a new test pattern selection method considering hazards. The concept of arrival time window is introduced and the concept of output deviation is redefined to accurately reflect the pattern capability on SDD detection. A new signal transition probability calculation method is presented to calculate output deviation more practical than that without considering hazards. Patterns from an N-detect test set for transition faults are then selected according to their output deviations. Experimental results show that, for the same pattern count, the patterns selected by the proposed method excite more long paths, and are capable of detecting more small delay defects at the early stage of delay testing compared to the method without considering hazards.

关键词： Hazards Circuit testing Circuit faults Automatic test pattern generation Delay effects Timing Clocks Propagation delay Logic testing Crosstalk

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A New Multiple-Round DOR Routing for 2D Network-on-Chip Meshes

A New Multiple-Round DOR Routing for 2D Network-on-Chip Mesh...

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Pacific Rim International Symposium on Dependable Computing

作者： Binzhang Fu Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

The Network-on-Chip (NoC) meshes are limited by the reliability constraint, which impels us to exploit the fault tolerant routing. Particularly, one of the main design issues is minimizing the loss of non-faulty routers at the presence of faults. To address that problem, we propose a new fault tolerant routing, which has the following two distinct advantages: First, it keeps a network deadlock-free by utilizing restricted intermediate nodes rather than adding virtual channels (VC). This characteristic leads to an area-efficient router. Second, in the proposed routing algorithm, the rounds of DOR are not limited by the number of VC's anymore. As a consequence, the number of sacrificed non-faulty routers is significantly reduced. We demonstrate above advantages through extensive simulations. The experimental results show that under the limitation of VC's, the proposed routing algorithm always sacrifices the minimal number of non-faulty routers compared to previous solutions.

关键词： Routing Network-on-a-chip Virtual colonoscopy Fault tolerance system recovery computer networks Region 4 Shape Laboratories computer architecture

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A Scalable Scan architecture for Godson-3 Multicore Microprocessor

A Scalable Scan Architecture for Godson-3 Multicore Micropro...

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Asian Test Symposium (ATS)

作者： Zichu Qi Hui Liu Xiangku Li Da Wang Yinhe Han Huawei Li Weiwu Hu Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (scalable mesh of crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (test access mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a data-synchronous-comparator (DSC) is proposed for comparing the scan responses of the identical cores.

关键词： Multicore processing Microprocessors Switches computer architecture system testing Laboratories Large-scale systems Linear predictive coding Delay Logic testing

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