检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

311 篇 会议
94 篇 期刊文献

馆藏范围

405 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

239 篇 工学
- 164 篇 计算机科学与技术...
- 97 篇 软件工程
- 65 篇 电子科学与技术（可...
- 40 篇 信息与通信工程
- 26 篇 机械工程
- 24 篇 控制科学与工程
- 17 篇 电气工程
- 12 篇 动力工程及工程热...
- 12 篇 生物工程
- 10 篇 仪器科学与技术
- 9 篇 交通运输工程
- 7 篇 光学工程
- 7 篇 材料科学与工程（可...
- 6 篇 建筑学
- 6 篇 土木工程
- 5 篇 航空宇航科学与技...
- 4 篇 冶金工程
- 3 篇 化学工程与技术
68 篇 理学
- 32 篇 数学
- 27 篇 系统科学
- 14 篇 物理学
- 11 篇 生物学
- 9 篇 统计学（可授理学、...
- 4 篇 化学
37 篇 管理学
- 32 篇 管理科学与工程(可...
- 16 篇 工商管理
- 7 篇 图书情报与档案管...
5 篇 医学
- 4 篇 临床医学
3 篇 经济学
- 3 篇 应用经济学
3 篇 法学
- 3 篇 社会学
3 篇 农学

主题

72 篇 computer archite...
41 篇 laboratories
33 篇 delay
27 篇 circuit faults
26 篇 hardware
23 篇 circuit testing
21 篇 costs
20 篇 bandwidth
20 篇 clocks
20 篇 system testing
18 篇 protocols
17 篇 microprocessors
16 篇 computer network...
15 篇 network-on-a-chi...
14 篇 switches
14 篇 automatic test p...
13 篇 parallel process...
13 篇 fault tolerance
13 篇 system-on-a-chip
12 篇 concurrent compu...

机构

95 篇 key laboratory o...
83 篇 key laboratory o...
38 篇 key laboratory o...
37 篇 graduate univers...
29 篇 beijing key labo...
29 篇 chinese academy ...
27 篇 institute of com...
21 篇 graduate univers...
16 篇 chinese academy ...
12 篇 key laboratory o...
12 篇 chinese academy ...
11 篇 loongson technol...
10 篇 graduate school ...
10 篇 key laboratory o...
9 篇 key laboratory o...
8 篇 department of co...
8 篇 beijing key labo...
8 篇 key laboratory o...
6 篇 school of comput...
6 篇 key laboratory o...

作者

58 篇 xiaowei li
31 篇 huawei li
30 篇 yu hu
28 篇 li xiaowei
20 篇 chen mingzhe
18 篇 yinhe han
16 篇 weiwu hu
15 篇 dongrui fan
14 篇 yang yang
14 篇 hu yu
13 篇 li huawei
13 篇 hong an
13 篇 sun ninghui
12 篇 han yinhe
12 篇 yin changchuan
11 篇 ninghui sun
11 篇 ge zhang
10 篇 fan dongrui
10 篇 saad walid
10 篇 李晓维

语言

372 篇 英文
29 篇 中文
4 篇 其他

检索条件"机构=Key Laboratory of Computer System and architecture"

共 405 条记录，以下是251-260 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A Low-Complexity Synchronization Based Cache Coherence Solution for Many Cores

A Low-Complexity Synchronization Based Cache Coherence Solut...

引用

International Conference on computer and Information Technology (CIT)

作者： Wei Lin DongRui Fan He Huang Nan Yuan XiaoChun Ye Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

computer architectures make a dramatic turn away from improving single-processor performance towards improved parallel performance through integrating many cores in one chip. However, providing directory based coherence protocols for these platforms is too complex and expensive. As a substitute, we propose a synchronization based cache coherence solution, which uses different cache policies according to three flexible software guided scopes (exclusion, producer and consumer scopes) to solve the data-race and coherence problem. Furthermore, this protocol implements word dirty bits (only one bit per word is needed in each L1 cache line) and a special hardware synchronization manager (HSM) to support multi-writer, the write-validate policy and to eliminate the remote un-cache spinning at the ldquoflagrdquo. We evaluate Godson-T, a platform supporting this protocol, against an idealized interleaved dual tag directory based protocol on the Splash2 and two bioinformatics benchmarks. The performance of the synch-based protocol is degraded only at 3.2% on average, but the real chip area is reduced at 32% even if the overhead of HSM is included.

关键词： Protocols computer architecture Hardware Concurrent computing Costs Network-on-a-chip Coherence Tiles Information technology Helium

来源：评论

学校读者我要写书评

暂无评论

Round-robin based scheduling algorithms for FIFO IQ switch

Round-robin based scheduling algorithms for FIFO IQ switch

引用

IEEE International Conference on Networking, Sensing and Control

作者： Xiao-jing Zhu Hong-bo Zeng Kun Huang Ge Zhang Department of Computer Science and Technology University of Science and Technology China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Network on chip (NoC) has become an active research area for high performance computer. Based on round-robin scheduling algorithm, we present three new scheduling algorithms for FIFO input queue (IQ) switches of network on chip, which are called rr-path, rr-dist and rr-al respectively, rr-path schedules the NoC traffic according to the distance between the source node and the destination node, and rr-dist schedules the NoC traffic according to the distance between the current and the destination nodes, and rr-al schedules the NoC traffic according to the difference between the arrival and the left flits numbers of every ports. We implement these algorithms in a network simulator, and analyze their performance using hotspot and uniform traffic patterns. Compared to round-robin scheduling algorithm, all of the new algorithms can reduce the max communication latency. In most cases, they can also reduce the average communication latency. Consequently, these new algorithms can improve the performance of multiprocessor systems.

关键词： Scheduling algorithm Network-on-a-chip Telecommunication traffic Traffic control Switches Round robin Processor scheduling Delay computer networks High performance computing

来源：评论

学校读者我要写书评

暂无评论

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors

Transparent dynamic binding with fault-tolerant cache cohere...

引用

International Conference on Dependable systems and Networks (DSN)

作者： Shuchang Shan Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level fault-tolerant approaches bind two cores to implement redundant execution and error detection. However, along with more cores integrated into one chip, existing static and dynamic binding schemes suffer from the scalability problem when considering the violation effects caused by external write operations. In this paper, we present a transparent dynamic binding (TDB) mechanism to address the issue. Learning from static binding schemes, we involve the private caches to hold identical data blocks, thus we reduce the global masters-lave consistency maintenance to the scale of the private caches. With our fault-tolerant cache coherence protocol, TDB satisfies the objective of private cache consistency, therefore provides excellent scalability and flexibility. Experimental results show that, for a set of parallel workloads, the overall performance of our TDB scheme is very close to that of baseline fault-tolerant systems, outperforming dynamic core coupling by 9.2%, 10.4%, 18% and 37.1% when considering 4, 8, 16 and 32 cores respectively.

关键词： Master-slave Fault tolerance Fault tolerant systems Coherence system-on-a-chip Pipelines

来源：评论

学校读者我要写书评

暂无评论

Diagnosis of multiple arbitrary faults with mask and reinforcement effect 10

Diagnosis of multiple arbitrary faults with mask and reinfor...

引用

Design, Automation and Test in Europe Conference and Exhibition

作者： Jing Ye Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9783981080162

We propose a multiple-fault diagnosis method with high diagnosability, resolution, first-hit and short run time. The method has no assumption on fault models, thus can diagnose arbitrary faults. To cope with the multiple-fault mask and reinforcement effect, two key techniques of construction and scoring of fault-tuple equivalence trees are introduced to choose and rank the final candidate locations. Experimental results show that, when the circuits have 2 arbitrary faults, the average diagnosability and resolution are 98% and 0.95, respectively, with the best case 100% and 1.00. Moreover, in average, even when 21 arbitrary faults exist, our method can still identify 93% of them with the resolution 0.78, increased by 41% and 39% in comparison with the latest work where the diagnosability and resolution are 66% and 0.56. Finally, 96% of our top-ranked candidate locations are actual fault locations.

关键词： Fault diagnosis Circuit faults Testing Fault location Integrated circuit yield Time to market Costs Automatic test pattern generation Test pattern generators Laboratories

来源：评论

学校读者我要写书评

暂无评论

Variation-Aware Scheduling for Chip Multiprocessors with Thread Level Redundancy

Variation-Aware Scheduling for Chip Multiprocessors with Thr...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Jianbo Dong Lei Zhang Yinhe Han Guihai Yan Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Thread-level redundancy in Chip Multiprocessors(TLR-CMP) is efficient for soft error tolerance. Process variation causes core-to-core (C2C) performance asymmetry across a chip, which should be taken into consideration for application scheduling. In this paper, two types of variations beyond C2C are introduced, i.e., inter-pair and intra-pair variation in TLR-CMP. Intra-pair performance asymmetry can affect the performance of applications differently. Based on the above observation, we firstly formalize the variation aware scheduling in TLR-CMP as a 0-1 programming problem,to maximize the system weighted throughput. An efficient scheduling algorithm, named IntraVarF&AppSen, is then proposed to tackle this problem, which can be proved to be optimal when the number of applications to be scheduled is equal to the number of core pairs. Simulation on a 64-core CMP shows 2.8%-4% improvement in weighted throughput when compared to prior VarF&AppIPC algorithm.

关键词： Yarn Job shop scheduling Redundancy Throughput Scheduling algorithm Cathode ray tubes computer architecture Error analysis Transistors Multiprocessing systems

来源：评论

学校读者我要写书评

暂无评论

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

引用

Asia and South Pacific Design Automation Conference

作者： Fei Wang Yu Hu Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

The amount of die area consumed by scan chains and scan control circuit can range from 15%~30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.

关键词： Circuit faults Combinational circuits Fault diagnosis Design for disassembly Circuit testing Software testing Signal processing Flip-flops Logic Laboratories

来源：评论

学校读者我要写书评

暂无评论

Desynchronize a legacy floating-point adder with operand-dependant delay elements

Desynchronize a legacy floating-point adder with operand-dep...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Jun Xu Hong Wang Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China University of the Chinese Academy of Sciences Beijing Beijing CN

De-synchronization is a fast and simple way to design an asynchronous circuit, but it has inherent limitation on performance improvement due to the traditional delay element implementation method. In this paper, a length-variable delay element is introduced to help us design a high performance asynchronous floating-point adder. The completion time can be automatically adjusted depending on the operation and operand; therefore, the useless waiting time and energy are effectively eliminated. The experimental result shows that our proposal has 33% performance advantages over the synchronous version and the traditional desynchronized implementation.

关键词： Delay Pipelines Adders Asynchronous circuits Synchronization Proposals

来源：评论

学校读者我要写书评

暂无评论

Utility analysis for Internet-oriented server consolidation in VM-based data centers

Utility analysis for Internet-oriented server consolidation ...

引用

IEEE International Conference on Cluster Computing

作者： Ying Song Yanwei Zhang Yuzhong Sun Weisong Shi Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Wayne State University Detroit USA

Server consolidation based on virtualization technology will simplify system administration, reduce the cost of power and physical infrastructure, and improve utilization in today's Internet-service-oriented enterprise data centers. How much power and how many servers for the underlying physical infrastructure are saved via server consolidation in VM-based data centers is of great interest to administrators and designers of those data centers. Various workload consolidations differ in saving power and physical servers for the infrastructure. The impacts caused by virtualization to those concurrent services are fluctuating considerably which may have a great effect on server consolidation. This paper proposes a utility analytic model for Internet-oriented server consolidation in VM-based data centers, modelling the interaction between server arrival requests with several QoS requirements, and capability flowing amongst concurrent services, based on the queuing theory. According to features of those services' workloads, this model can provide the upper bound of consolidated physical servers needed to guarantee QoS with the same loss probability of requests as in dedicated servers. At the same time, it can also evaluate the server consolidation in terms of power and utility of physical servers. Finally, we verify the model via a case study comprised of one e-book database service and one e-commerce Web service, simulated respectively by TPC-W and SPECweb2005 benchmarks. Our experiments show that the model is simple but accurate enough. The VM-based server consolidation saves up to 50% physical infrastructure, up to 53% power, and improves 1.7 times in CPU resource utilization, without any degradation of concurrent services' performance, running on Rainbow - our virtual computing platform.

关键词： Web server Costs Web and internet services Queueing analysis Upper bound Databases Web services Resource management Degradation Concurrent computing

来源：评论

学校读者我要写书评

暂无评论

Design of New Hash Mapping Functions

Design of New Hash Mapping Functions

引用

International Conference on computer and Information Technology (CIT)

作者： Fenglong Song Zhiyong Liu Dongrui Fan Junchao Zhang Lei Yu Nan Yuan Wei Lin Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Conflict can decrease performance of computer severely, such as bank conflicts reduce bandwidth of interleave multibank memory systems and conflict misses reduce effective on-chip capacity, and this incurs much conflict miss further. Conflicts can be avoided by a suitable address mapping scheme which maps the most frequently occurring patterns conflict-free. In this paper, we present a new XOR-based mapping scheme, called XORM, which focuses on multi-bank shared cache of on-chip many-core architecture. The XORM mapping scheme can map arbitrary bits of address to set indices and compute each set index bit as XOR of a transpositional subset of the bits in the address. Then, we analyze necessary characteristics of an address mapping scheme to avoid conflict in many-core architecture. Next, we give a case study to design optimal hash functions based on XORM scheme for skewed-associative cache. Finally, we introduce another case study, in which we illustrate how to design an XORM mapping scheme with lower implementation cost, complexity and computing latency in shared cache of chipped many-core architecture. The evaluated results show the effectiveness of XORM mapping scheme.

关键词： computer architecture Delay Bandwidth Costs Information technology Laboratories system-on-a-chip Hardware High performance computing Polynomials

来源：评论

学校读者我要写书评

暂无评论

Address Remapping for Static NUCA in NoC-Based Degradable Chip-Multiprocessors

Address Remapping for Static NUCA in NoC-Based Degradable Ch...

引用

Pacific Rim International Symposium on Dependable Computing

作者： Ying Wang Lei Zhang Yinhe Han Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Large scale Chip-Multiprocessors (CMPs) generally employ Network-on-Chip (NoC) to connect the last level cache (LLC), which is generally organized as distributed NUCA (non-uniform cache access) arrays for scalability and efficiency. On the other hand, aggressive technology scaling induces severe reliability problems, causing on-chip components (e.g., cores, cache banks, routers) failure due to manufacture defects or on-line hardware faults. Typical degradable CMPs should possess the ability to work around defects by disabling faulty components. For static NUCA architecture, when cache banks attached to a computing node are disabled, however, certain physical address sections will no longer be accessible. Prior approaches such as sets reduction introduced in Intel Xeon processor 7100 series enable turning off cache banks by masking certain sets bits in physical address1, which greatly wastes cache capacity. In this paper, we propose to tackle the above problem in a finer granularity to restrict the capacity loss in NUCA cache. Cache accesses to isolated nodes are redirected based on the utility-driven address remapping scheme that reduces data blocks conflicts in fault-tolerant shared-LLC. We evaluate our technique using GEMS simulator. Experimental results show that address remapping achieves significant improvement over the conventional cache sizing scheme.

关键词： Tiles Nickel Hardware Fault tolerance Fault tolerant systems Prediction algorithms computer architecture

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共41页 << < 22 23 24 25 26 27 28 29 30 31 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：