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Design of a flip-flop circuit within digital logic analyzer based on FPGA

Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology 2009年第SUPPL. 1期41卷 58-62页

作者： Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.

关键词： Field programmable gate arrays (FPGA)

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Register pressure sensitive instruction speculative scheduling technology

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第3期46卷 485-491页

作者： Huang, Lei Feng, Xiaobing Lü, Fang Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Speculation is an important method to overcome control flow constraints during instruction scheduling. On the one hand, speculation can exploit more instruction-level parallelism and improve performance. However, on the other hand, it may also lengthen the live range of variables and increase the register pressure, which in turn results in spilling some variables to memory and deteriorating the performance. Previous work on register pressure sensitive instruction scheduling generally scheduled instructions conservatively when there were too many live variables in the scheduling region. But actually different variables have different spilling costs and different impacts on performance. Here a register pressure sensitive speculative instruction scheduling technology is presented, which not only considers the count of live variables, but also analyzes the benefits and the spilling costs brought by instructions' speculative motions. The decrement of cycles in critical path is calculated as benefit, while the spilled variables are predicted and their spilling cost is used as cost. Only the speculative motion with benefit greater than the cost is permitted in our method. This algorithm has been implemented in Godson Compiler for MIPS architecture. Experiment result shows that the method in this paper can obtain 1.44% speedup on average relative to its register pressure insensitive counterpart on SPEC CPU2000INT benchmarks.

关键词： Costs

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A study and implementation of the Huffman algorithm based on condensed Huffman table

A study and implementation of the Huffman algorithm based on...

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International Conference on computer Science and Software Engineering, CSSE 2008

作者： Bao, Ergude Li, Weisheng Fan, Dongrui Ma, Xiaoyu School of Software Beijing Jiaotong University Key Laboratory of Computer System and Architecture Institute of Computer Technology Chinese Academy of Sciences

ISBN: (纸本)9780769533360

Huffman codes are being widely used as a very efficient technique for compressing data. To achieve high compressing ratio, some properties of encoding and decoding for canonical Huffman table are discussed. A study and implementation of the Huffman algorithm based on condensed Huffman table is studied. New condensed Huffman table could reduce the cost of the Huffman coding table. Compared with traditional Huffman coding table and other improved tables, the best advantages of new condensed Huffman table is that the space requirement is reduced significantly. © 2008 IEEE.

关键词： Codes (symbols)

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Profile guided optimization for dataflow predication

Profile guided optimization for dataflow predication

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Li, Wang Hong, An Yongqing, Ren Yaobin, Wang Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Sciences Beijing 100080 China

ISBN: (纸本)9781424426836

Dataflow predication provides a lightweight full support for predicated execution in dataflow-like architectures. One of its major overhead is the large amounts of fanout trees for distributing predicates to all dependant instructions. Conventional optimizations are predicating only the heads or tails of dataflow chains. Predicating tails offers more speculation but leads to resource contentions and power consumption increasing. Predicating heads is power efficient but reduces speculation and instruction level parallelism. This paper introduces a profile guided technique to combine these optimizations. It uses profiling feedback to guide the compiler in deciding to predicate at the head or tail. By predicating tails on hot paths and predicating heads on infrequent paths, this technique can get performance, power and resource efficiency Performance evaluation result shows that profile guided optimization performs better in removing fanout trees. It has 10.6% speedup over always predicating heads and 2.5% speedup over always predicating tails in performance. © 2008 IEEE.

关键词： Forestry

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A Wire delay scalable stream processor architecture

A Wire delay scalable stream processor architecture

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Guang, Xu Hong, An Ming, Cong Fang, Wang Yongqing, Ren Department of Computer Science and Technology University of Science and Technology of China Hefei 230026 China Key Laboratory of Computer System and Architecture Chinese Academy of Science Beijing 100080 China

ISBN: (纸本)9781424426836

Growing on-chip wire delays will cause many future microarchitecture to be distributed. The centralized control and data transmission of the conventional stream processor need to be improved, the hardware resources within a single stream processor become tiles on one or more switched micronetworks. In this paper, we introduce the architecture of the tiled stream processor which aims to adapt to the increasing wire resistance. The tiled stream processor consists of tile arrays, the distributed control and data network which connect tiles. The tile arrays include the five type of reused tiles, the control packet transferred in the control network traverse the tile in a cycle. The architecture of the tiled stream processor supports explicit data management in the hardware way and include two level register hierarchy which are controlled by the software to capture the data locality. The tiled stream processor use the stream programming model which are StreamC/KernelC language, the kernel microcode executed in the tiled arrays are statically scheduled into instruction blocks and execute dynamically in an dataflow order. Finally, we discuss features that affect the kernel performance, with the one cycle routing delay the simulator can achieve an average of 10IPC in eight kernels. © 2008 IEEE.

关键词： computer architecture

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A Self-Repairable Microprocessor

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ECS Transactions 2009年第1期18卷

作者： Yuanjiang Xie Xiang Fu Zijian He Yang Zhao Yu Hu Xiaowei Li Institute of Computing Technology Chinese Academy of Sciences Department of Computer Science and Engineering University of California Riverside Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences No. 6 Ke-Xue-Yuan South Road Beijing Beijing 100190 China

With increasing defect density, microprocessors, especially the embedded caches, will encounter more faults. Adding spare resources to replace defective components is a widely accepted method for yield enhancement. In this work, a repair method using content addressable memory combined with spare bits, as well as a novel fault injection method is proposed. With the proposed fault injection technique, various numbers and types of faults can be flexibly injected into the silicon. A wireless sensor network system using our self-repairable microprocessor (SRP) is developed to prove the effectiveness of the proposed technique.

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Robust test generation for power supply noise induced path delay faults

Robust test generation for power supply noise induced path d...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Fu, Xiang Li, Huawei Hu, Yu Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Graduate School Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds. ©2008 IEEE.

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Diva: A dataflow programming model and its runtime support in java virtual machine

Diva: A dataflow programming model and its runtime support i...

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13th IEEE Asia-Pacific computer systems architecture Conference, ACSAC 2008

作者： Yang, Chen Bin, Fan Lujie, Zhong Chengyong, Wu Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate School of the Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424426836

Microprocessors have turned to multicore, i.e. multiple processor cores, along with some levels of on-chip caches and interconnection networks, integrated on a singe chip. However, it brings challenges on how to program these processors effectively and efficiently, which is known as the "Programming Wall". This paper proposes a systematic approach to attack the problem. We describe an extension of Java programming language with dataflow paradigm and transactional memory. Our approach alleviates the difficulties of parallel programming by providing a higher level of abstraction and relieving programmers of low-level threading and locking details. We also describe the design of a runtime system to support and optimize for the extension. We have implemented a prototype based on Apache Harmony DRL Virtual Machine. Preliminary experimental results on a 16-core SMP machine show that our approach achieves reasonable scalability and can adapt to the variance of available hardware resources. © 2008 IEEE.

关键词： Parallel programming

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A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults

A design- for-diagnosis technique for diagnosing both scan c...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Wang, Fei Hu, Yu Li, Huawei Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Science Beijing China Graduate University Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781424419227

The amount of die area consumed by scan chains and scan control circuit can range from 15%∼30%, and scan chain failures account for almost 50% of chip failures. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a design-for-diagnosis (DFD) technique is proposed to diagnose faulty scan chains precisely and efficiently, moreover, with the assistant of the proposed technique, the conventional logic diagnostic process can be carried on with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can still be applied to our design. Experiments on ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique. ©2008 IEEE.

关键词： Chains

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Localized random access scan: Towards low area and routing overhead

Localized random access scan: Towards low area and routing o...

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2008 Asia and South Pacific Design Automation Conference, ASP-DAC

作者： Hu, Yu Fu, Xiang Fan, Xiaoxin Fujiwara, Hideo Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100080 China 8916-5 Takayama Ikoma Nara 630-0192 Japan

ISBN: (纸本)9781424419227

Conventional random access scan (RAS) designs, although economic in test power dissipation, test application time and test data volume, are expensive in area and routing overhead. In this paper, we present a localized RAS architecture (LRAS) to address this issue. A novel scan cell structure, which has fewer transistors than the multiplexer-type scan cell, is proposed to eliminate the global test enable signal and to localize the row enable and the column enable signals. Experimental results on ISCAS'89 and ITC'99 benchmark circuits demonstrate that LRAS has 54% less area overhead than multiplexer-type scan chain based designs, while significantly outperforms the state-of-the-art RAS scheme in routing overhead. ©2008 IEEE.

关键词： Multiplexing equipment

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