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Asia and South Pacific Design Automation Conference

作者： Xiang Fu Huawei Li Yu Hu Xiaowei Li Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences China

ISBN: (纸本)9781424419210

In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.

关键词： Noise robustness Power generation Power supplies Noise generators Delay Circuit testing Circuit faults Timing Switches Feeds

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Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor

Fetching Primary and Redundant Instructions in Turn for a Fa...

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Pacific Rim International Symposium on Dependable Computing

作者： Shijian Zhang Weiwu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

With the development of semiconductor technology, microprocessors become more and more susceptible to transient faults. Some proposed schemes support redundant execution of a program in a superscalar processor for fault tolerance. However, they require a huge queue to accommodate interim states, which enlarge the hardware cost significantly. This paper analyzes the effect of halving a processor¿s instruction fetch bandwidth on a program¿s performance. We find that the performance degradation resulted from halving instruction fetch bandwidth declines when instruction latency is lengthened, branch prediction accuracy deteriorates or cache miss rate increases. Since an embedded microprocessor is characterized by long instruction latency, high branch misprediction rate and cache miss rate, a fault-tolerant scheme is proposed, in which two threads fetch instructions in turn and execute in the same processor core simultaneously without any extra queue. The simulation results from eight embedded applications show that performance penalty of our solution ranges from 6.5% to 30.1%, with an average of 22.5%, which is lower than that of the other proposed schemes. The experiment also indicates that our scheme can effectively detect faults occurring in the entire pipeline with short fault detection latency and minimal hardware cost. It is well suited for our solution to realize a reliable embedded microprocessor.

关键词： Fault tolerance Microprocessors Delay Hardware Costs Bandwidth Fault detection Performance analysis Degradation Accuracy

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Instruction level test for parallel multipliers

Instruction level test for parallel multipliers

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15th IEEE International Conference on Electronics, Circuits and systems, ICECS 2008

作者： Lin, Ma. Yan, Gao Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences P.O. Box 2704-25 Beijing 100190 China College of Electronics and Information Engineering Tongji University SiPing Road 1239 Shanghai 200092 China Graduate University of Chinese Academy of Science Beijing 100049 China

ISBN: (纸本)9781424421824

Multiplication operations are the normal operations in operating systems or scientific calculations. Multipliers embedded in processors, DSP or SoC are well optimized for best performance, and they are sensitive to test overhead. Instruction level test is a popular functional test approach for microprocessors test, and it can get satisfactory test results. But for the multipliers, one important part of microprocessors, there is no detail on how to testing them. This paper presents an instruction level test approach for the multiplier test. The proposed approach does not modify the multipliers and does not need any extra logic just using instructions of the processors to test processors' multipliers. Sequentially it does not have any test cost on area or timing. Moreover the instruction-level test is suited for at-speed test in nature. Experimental results on the real processor's circuits show that the instruction level test approach has good effect on parallel multipliers © 2008 IEEE.

关键词： system-on-chip

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Channel Width Utilization Improvement in Testing NoC-Based systems for Test Time Reduction

Channel Width Utilization Improvement in Testing NoC-Based S...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Jia Li Qiang Xu Yu Hu Xiaowei Li Key Laboratory of Computer System and Architecture ICT CAS Beijing China Department of Computer Science & Engineering Chinese University of Hong Kong Hong Kong China Chinese Academy and Sciences Beijing China

Testing NoC-based systems mainly relies on reusing the Network-on-Chip architecture as the test access mechanism (TAM). This, however, implies that the core's test wrapper is supplied with full NoC channel width even if there is a mismatch between the two. How to effectively and efficiently make better utilization of the NoC channels for test data transferring is therefore an interesting and challenging problem. In this paper, we propose to combine a new wrapper design with interleaved test scheduling. Compared to [8], the proposed method can achieve better NoC channel utilization for test without manipulating test frequencies, which not only reduces test power, but also saves design effort for the test engineers. Consequently, the testing time of the NoC-based system is considerably reduced with the proposed technique (especially under stringent power constraints), as shown in the experimental results on circuits crafted from ITC02 benchmarks.

关键词： system testing Network-on-a-chip Circuit testing system-on-a-chip Electronic equipment testing Frequency Logic testing Clocks Application software Content addressable storage

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor

A Case Study on At-Speed Testing for a Gigahertz Microproces...

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IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Da Wang Rui Li Yu Hu Huawei Li Xiaowei Li Chinese Academy and Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics Company Limited Shanghai China

This paper describes a low cost, high quality at-speed testing strategy implemented on a gigahertz microprocessor with multi-clock domains. The presented DFT method not only utilizes the internal phase-locked loops (PLLs) to provide complex test clock sequences, but also applies a hybrid scan compression structure to reduce test data volume. It is difficult and time-consuming to generate at-speed tests for a design with embedded memories and multi-clock domains. The proposed test pattern generation scheme can gain transition fault coverage of approximately 83% for this high-performance microprocessor, and the test power consumption is well controlled.

关键词： Microprocessors Circuit testing Clocks Logic testing system testing Electronic equipment testing Test pattern generators Costs Circuit faults Energy consumption

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Frequency method to study the propagation of transient fault in combinational logic

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2008年第5期20卷 605-611+617页

作者： Lei, Shaohua Han, Yinhe Li, Xiaowei Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

This paper presents a frequency analysis method to analyze the propagation procedure of transient error in combinational logic. By using the Fourier transform with the input signal and the frequency feature of combination circuit, the output can be obtained after frequency-domain computing. A model is proposed in this paper to deal with the signals which drive the combinational logic gates working at nonlinear region. The frequency analysis method is able to provide higher accuracy, while significantly speeding up simulations. Experimental results prove that our approach is several orders of magnitude faster than HSPICE, under the guarantee of approximately 93% accuracy (compared to HSPICE).

关键词： LSI circuits

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A HyperTransport-based personal parallel computer

A HyperTransport-based personal parallel computer

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IEEE International Conference on Cluster Computing

作者： Xiaojun Yang Fei Chen Hailiang Cheng Ninghui Sun Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Chinese Academy and Sciences Beijing China

Instead of all using commodity components, an approach building a personal parallel computer on top of a non-coherent HyperTransport (HT) fabric is presented in the paper. The advantage is to provide both lower cost and higher performance compared with the existing method. A HT switch is designed and implemented for the interconnection of a set of AMD Opteron processors for building an in-a-box cluster. On our prototyping system, the result of evaluation experiments shows this approach gives the better performance.

关键词： Switches Program processors computers Bandwidth Fabrics Protocols computer architecture

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A novel hint-based I/O mechanism for centralized file server of cluster

A novel hint-based I/O mechanism for centralized file server...

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IEEE International Conference on Cluster Computing

作者： Huan Chen Jin Xiong Ninghui Sun Chinese Academy of Sciences Beijing China Institute of Computing Technology Chinese Academy and Sciences Beijing China Key Laboratory of Computer Architecture and System Chinese Academy and Sciences Beijing China

In the medium and small cluster systems, the centralized file server such as NFS is the main approach to provide the storage service with low cost and easy management. However, when multiple parallel applications access the shared storage at the same time, the I/O performance decreases much because of the interference of the I/O requests coming from the different clients. In this paper, a hint-based I/O mechanism is proposed and implemented in the United-FS. By analyzing the hint information of the I/O requests, the related requests are grouped, sorted and scheduled by our hint-based I/O scheduler. The experiments show that our hint-based I/O mechanism nearly doubles the read performance compared with NFS, and has better scalability.

关键词： File systems Servers File servers Performance evaluation Bandwidth Scalability Time factors

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On reducing both shift and capture power for scan-based testing

On reducing both shift and capture power for scan-based test...

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Asia and South Pacific Design Automation Conference

作者： Jia Li Qiang Xu Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong China Key Laboratory of Computer System and Architecture ICT Chinese Academy and Sciences Beijing China

ISBN: (纸本)9781424419210

Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-fllling technique to reduce both shift power and capture power during scan tests, namely LSC-filling . The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT's average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS'89 benchmark circuits show the effectiveness of the proposed methodology.

关键词： Circuit testing Energy consumption Power dissipation system testing Electrical fault detection Fault detection Circuit faults Benchmark testing Laboratories Power engineering computing

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On capture power-aware test data compression for scan-based testing 08

On capture power-aware test data compression for scan-based ...

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IEEE International Conference on computer-Aided Design

作者： Jia Li Xiao Liu Yubin Zhang Yu Hu Xiaowei Li Qiang Xu Chinese Academy and Sciences Beijing China CUhk REliable computing laboratory (CURE) Department of Computer Science & Engineering Chinese University of Hong Kong New Territories Hong Kong China Key Laboratory of Computer System and Architecture ICT CAS Beijing China

ISBN: (纸本)9781424428205

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the ldquodonpsilat-carerdquo bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

关键词： Test data compression Circuit testing Integrated circuit testing system testing Benchmark testing Automatic testing Laboratories Power engineering computing Power system reliability Integrated circuit technology

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