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Asian Test Symposium (ATS)

作者： Jing Ye Xiaolin Zhang Yu Hu Xiaowei Li Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

Volume diagnosis plays an important role in the yield learning process. To get a high quality diagnosis result, patterns with high distinguish ability are essential. However, the test patterns used by volume diagnosis commonly have low distinguish ability to specific faults. In our experiments, we observe that on average, under automatic generated test patterns, faults in the same fan out free region (FFR) account for only 6% of all possible fault pairs, but their share in total indistinguishable faults is 70%, faults in different FFRs but with the same observation points account for 4% of all fault pairs, but their share in total indistinguishable faults is 22%. Exploiting this fact that faults in the same FFRs are harder to be distinguished, we propose an Automatic Diagnostic Pattern Generation (ADPG) method named Substantial Fault Pairs at-A-Time (SFPAT)-ADPG. By applying a transformed circuit and a new fault list to an existing Automatic Test Pattern Generation (ATPG) tool, we generate the compressed test patterns which are also the diagnostic patterns with high distinguish ability for the original circuit. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the effectiveness of the proposed SFPAT-ADPG method.

关键词： Circuit faults Automatic test pattern generation Benchmark testing Logic gates Transforms Integrated circuit modeling

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Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power

Design of Low-Cost High-Performance Floating-Point Fused Mul...

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International Conference on VLSI Design

作者： Zichu Qi Qi Guo Ge Zhang Xiangku Li Weiwu Hu Chinese Academy and Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Chinese Academy of Sciences Beijing Beijing CN

ISBN: (纸本)9781424455416

This paper presents a floating-point fused multiply-add (FMA) unit with low-cost and low power techniques. To improve the performance, two single-precision operations can be performed concurrently with one double-precision datapath, which is very useful in multimedia and even scientific applications. Moreover, to reduce the additional area costs for supporting two single-precision operations in parallel, multiple double-precision units, i.e., the multiplier, shifter and adder, are reused as much as possible. A modified dual-path algorithm is proposed by classifying the exponent difference into three cases and implementing them with close and far paths, which can reduce latency and facilitate lowering power consumption by enabling only one of the two paths. In addition, in case of FADD instructions, the multiplier in the first stage is bypassed and kept in stable mode, which can significantly improve FADD instruction performance and lower power consumption. The overall FMA unit has a latency of 4 cycles while the FADD operation has 3 cycles. Each cycle has a time delay of about 0.66 ns in the ST 65 nm CMOS technology. Compared with the conventional double-precision FMA, about 13% delay is reduced and about 22% area is increased, which is acceptable since two single-precision results can be generated simultaneously.

关键词： Costs Energy consumption CMOS technology Hardware Throughput Very large scale integration Laboratories computer architecture Delay effects Roundoff errors

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Interference-aware relay selection scheme in cooperative relay networks

Interference-aware relay selection scheme in cooperative rel...

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International Symposium on Wireless Personal Multimedia Communications (WPMC)

作者： Jinlong Cao Tiankui Zhang Zhimin Zeng Dantong Liu Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing China School of Electronic Engineering and Computer Science Queen Mary University of London London UK

ISBN: (纸本)9781479904631;9781479904631

Relay selection scheme with multiple source-destination pairs and multiple potential relays in cooperative relay networks considering co-channel interference (CCI) is proposed in this paper. In cooperative relay networks, which relay nodes are selected has great impact on the system performance. It is an optimization problem for selecting suitable relay nodes. The exhaustive search can solve this problem but the complexity will increase factorially with the network size, i.e., the number of source-destination pairs and the number of relays in the network. This paper proposes a novel quantum particle swarm optimization (QPSO) based relay selection scheme which can maximize the system throughput of the cooperative relay networks but has less computational complexity. Simulation results show that QPSO based relay selection scheme has the ability to search global optimal solution compared with other relay selection schemes in the literature.

关键词： Convergence Complexity theory

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Dynamic register promotion of stack variables 11

Dynamic register promotion of stack variables

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International Symposium on Code Generation and Optimization (CGO)

作者： Jianjun Li Chenggang Wu Wei-Chung Hsu Graduate University of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China Deparunent of Computer Science National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781612843568

Dynamic Binary Translation (DBT) has been widely used in various applications. Although new architectures and micro-architectures often create performance opportunities for programmers and compilers, such performance opportunities may not be exploited by legacy executables. For example, the additional general-purpose and XMM registers in the Intel64 architecture do not benefit the IA-32 binaries. In this paper, we designed and developed a DBT system to dynamically promote stack variables in the source binaries to the additional registers of the target architecture. One of the most challenging problems is how to deal with the possible but rare memory aliases between promoted stack variables and other implicit memory references. We devised a runtime alias detection approach based on the page protection mechanism in Linux and a novel stack switching method to catch memory aliases at run-time. This approach is much less expensive than traditional approaches like inserting address checking instructions. On an Intel64 platform, our DBT system with speculative stack variable promotion has sped up several SPEC CPU2006 benchmarks in IA-32 code, with the largest performance gain over 45%.

关键词： Registers Optimization Switches computer architecture Benchmark testing Runtime Program processors

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Interference-aware multi-user relay selection scheme in cooperative relay networks

Interference-aware multi-user relay selection scheme in coop...

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IEEE Globecom Workshops

In cooperative relay networks with multiple users and multiple potential relays, which relay nodes are selected has great impact on the system performance. It is an optimization problem for selecting suitable relay nodes. The exhaustive search can solve this problem but the complexity will increase factorially with the network size, i.e., the number of users and the number of relays in the network. In this paper, we formulate both single-objective and multi-objective relay selection problems. For single-objective relay selection problem, only system throughput or fairness is considered. A novel quantum particle swarm optimization (QPSO) based relay selection scheme is proposed. For multi-objective relay selection problem, two contradictive objectives, i.e., system throughput and fairness are considered simultaneously. A novel non-dominated sorting quantum particle swarm optimization (NSQPSO) based relay selection scheme is proposed. Simulation results show that the proposed relay selection schemes have the ability to search global optimal solution but have less computational complexity compared with exhaustive search.

关键词： Tin Optimization Interference Signal to noise ratio Sociology

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A QoE-Driven FEC Rate Adaptation Scheme for Scalable Video Transmissions over MIMO systems

A QoE-Driven FEC Rate Adaptation Scheme for Scalable Video T...

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IEEE International Conference on Communications

作者： Xiang Chen Haiqing Du Jenq-Neng Hwang James A. Ritcey Chung-Nan Lee Department of Electrical Engineering University of Washington Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Department of Computer Science and Engineering National Sun Yat-Sen University

ISBN: (纸本)9781467364300

We propose a forward error correction (FEC) coding rate adaptation scheme which maximizes the quality of experience (QoE), for scalable video coding (SVC) based video transmissions over multi-input multi-output (MIMO) systems. The proposed scheme adaptively selects the best set of spatial channels, number of video layers and their corresponding FEC coding rate according to channel state information (CSI) from the receiver. Unlike previous work, our proposed scheme distributes the FEC encoded bit streams to multiple spatial channels so that additional diversity gains can be obtained. Due to the complexity of the optimization, we decompose the original problem into several sub-problems, which can then be solved by a heuristic algorithm. The optimal solution can be found by choosing the best among all the candidate solutions obtained from the sub-problems. The effectiveness and superb performance of our proposed scheme can be demonstrated by many simulations with different videos and channel conditions.

关键词： FEC QoE SVC MIMO Rate adaptation

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A service-oriented priority-based resource scheduling scheme for virtualized utility computing 08

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Proceedings of the 15th international conference on High performance computing

作者： Ying Song Yaqiong Li Hui Wang Yufang Zhang Binquan Feng Hongyong Zang Yuzhong Sun Key Lab. of Computer System and Architecture Inst. of Computing Techn. Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China and Graduate Univ. of Chinese Academy of Sciences China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences China and National Research Center for Intelligent Computing Systems ICT China

ISBN: (纸本)9783540898931

In order to provide high resource utilization and QoS assurance inutility computing hosting concurrently various services, this paper proposes aservice computing framework-RAINBOW for VM(Virtual Machine)-basedutility computing. In RAINBOW, we present a priority-based resourcescheduling scheme including resource flowing algorithms (RFaVM) to optimizeresource allocations amongst services. The principle of RFaVM is preferentiallyensuring performance of some critical services by degrading of others to someextent when resource competition arises. Based on our prototype, we evaluateRAINBOW and RFaVM. The experimental results show that RAINBOWwithout RFaVM provides 28%-324% improvements in service performance,and 26% higher the average CPU utilization than traditional service computingframework (TSF) in typical enterprise environment. RAINBOW with RFaVMfurther improves performance by 25%-42% for those critical services whileonly introducing up to 7% performance degradation to others, with 2%-8%more improvements in resource utilization than RAINBOW without RFaVM.

关键词： resource scheduling utility computing virtualization

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Automatic Selection of Internal Observation Signals for Design Verification

Automatic Selection of Internal Observation Signals for Desi...

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IEEE VLSI Test Symposium (VTS)

作者： Tao Lv Hua-wei Li Xiao-wei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences

ISBN: (纸本)9781424437696

As the design complexity increases dramatically, results of functional simulation are usually checked through only a part of signals during design verification. It is important, therefore, to consider the observability of internal signals for effective checking. This paper proposes a static observability analysis method to automatically select internal observation signals, which improves the quality of functional verification. A series of formulas are defined to evaluate observability of internal signals, and an algorithm is proposed to locate the sources of low-observability. Such sources, rather than general hard-to-observe signals, are desirable internal observation signals. Experimental results indicate that signals selected by this method can improve the observability of designs more than those randomly selected from hard-to-observe signals.

关键词： Internal observation signals Design verification Static analysis

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P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime Reliability Analysis Framework

P2CLRAF: An Pre-and Post-silicon Cooperated Circuit Lifetime...

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2010 19th IEEE Asian Test Symposium(第19届IEEE亚洲测试技术学术会议 ATS 2010)

作者： Song Jin Yinhe Han Huawei Li Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing P.R. China Graduate University of Chinese Academy of Sciences Beijing P.R. China

Statistical static timing analysis (SSTA) considering process variation and aging effects is usually used to analyze circuit lifetime reliability at design phase. A key challenge for statistical lifetime reliability analysis is that an accurate statistical timing model is needed to carefully model practical variation distribution as well as delay correlation. In this work, P2CLRAF, a circuit lifetime reliability analysis framework is proposed. It calibrates presilicon SSTA result by learning the collected data from path delay testing at post-silicon timing validation phase. A neural network inside P2CLRAF is trained to learn variation distribution and delay correlation based on the statistic of path delay testing. The learned information is then fed back to SSTA to further improve the accuracy of circuit lifetime reliability analysis. Experimental results demonstrate the effectiveness of the proposed analysis framework.

关键词： Lifetime Reliability Process Variation NBTI

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Analysis of Memory Capacity for Deep Echo State Networks

arXiv

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arXiv 2019年

作者： Liu, Xuanlin Chen, Mingzhe Yin, Changchuan Saad, Walid Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing China Wireless@VT Bradley Department of Electrical and Computer Engineering Virginia Tech BlacksburgVA United States

—In this paper, the echo state network (ESN) memory capacity, which represents the amount of input data an ESN can store, is analyzed for a new type of deep ESNs. In particular, two deep ESN architectures are studied. First, a parallel deep ESN is proposed in which multiple reservoirs are connected in parallel allowing them to average outputs of multiple ESNs, thus decreasing the prediction error. Then, a series architecture ESN is proposed in which ESN reservoirs are placed in cascade that the output of each ESN is the input of the next ESN in the series. This series ESN architecture can capture more features between the input sequence and the output sequence thus improving the overall prediction accuracy. Fundamental analysis shows that the memory capacity of parallel ESNs is equivalent to that of a traditional shallow ESN, while the memory capacity of series ESNs is smaller than that of a traditional shallow ESN. In terms of normalized root mean square error, simulation results show that the parallel deep ESN achieves 38.5% reduction compared to the traditional shallow ESN while the series deep ESN achieves 16.8% reduction. Copyright © 2019, The Authors. All rights reserved.

关键词： Network architecture

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