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Physical-annotation-based power modeling and estimation method for processor

Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第11期19卷 1471-1475页

作者： Huang, Kun Zhang, Ge Wang, Jun Zeng, Hongbo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.

关键词： High performance processor Physical annotation Power estimation Power modeling

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Innovative architecture-level power estimation methodology for godson processor

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第5期44卷 782-789页

作者： Huang, Kun Zhang, Longbing Hu, Weiwu Zhang, Ge Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.

关键词： Microprocessor chips

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Study on blocked LU decomposition on many-core architecture

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Gaojishu Tongxin/Chinese High Technology Letters 2011年第3期21卷 248-253页

作者： Yu, Lei Liu, Zhiyong Ma, Yike Song, Fenglong Xu, Weizhi Ye, Xiaochun Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University of Chinese Academy of Sciences Beijing 100039 China

The authors studied the scientific application LU decomposition deeply. A speedup model for LU decomposition was proposed, and an algorithm for LU decomposition based on bit reverse xor (BRX) was implemented. Then a dynamic absolute balance policy (DABP) algorithm was presented. In order to estimate the algorithms of 2 dimensional (2D) scatter, BRX and DABP, two different estimation functions were given and they were used to estimate the load balance problem of the algorithms. These two functions verify that the DABP algorithm has the best load balance. The simulations of the three algorithms were performed on the many-core architecture Godson-T. The experiments prove that the speedup of the DABP algorithm is 46 and it is the best performance of the three algorithms.

关键词： computer architecture

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Tradeoff cache between latency and capacity in chip multiprocessors

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第1期46卷 167-175页

作者： Xiao, Junhua Feng, Zijun Zhang, Longbing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate School Chinese Academy of Sciences Beijing 100049 China

Chip multiprocessors (CMP) have become the main stream microprocessor architecture. In CMP, the cache, especially the last level cache, is the critical part of its performance and becomes a focus of current research activities. CMP cache faces the conflicting requirements of satisfying both latency and capacity, and has to trade off between techniques that reduce off-chip and cross-chip misses. The private cache design minimizes the cache access latency but reduces the total effective cache capacity. The shared cache design maximizes the effective cache capacity but incurs long hit latency. In this paper, a CMP cache design (tradeoff cache between latency and capacity, TCLC) is proposed. TCLC is a private and shared hybrid design. TCLC can dynamically identify the cache blocks' shared type and optimize them respectively. The private type is optimized through migration policy, the shared read-only type is optimized through replication policy, and the shared read-write type is optimized through center placement policy. TCLC tries to make cache access latency close to private design, and effective cache capacity close to shared design, which can mitigate the impact of the wire delay and reduce the average memory access latency. The experiment results indicate that this proposal performs 13.7% better than a private cache and 12% better than a shared cache.

关键词： Economic and social effects

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Address register promotion method based on feedbacks

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2009年第4期46卷 698-704页

作者： Zhang, Chao Lü, Fang Wang, Lei Feng, Xiaobing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China Graduate University Chinese Academy of Sciences Beijing 100049 China

In processor architectures such as MIPS, ALPHA, SPARC and PowerPC, indirect addressing mode is always adopted to access global variables and static ones. Since the addresses of these variables and the corresponding values are in different data sections in the corresponding binary file, the data locality of the program will be very poor. As a result, accessing the read only addresses of these variables every time tends to result in non-trivial redundant data cache miss memory accesses. Moreover, such indirect addressing mode will generate two sequential load instructions which have data dependences between them. As a result, the amount of instruction level parallelism (ILP) of the program will be decreased. The authors present an address register promotion method based on feedbacks (ARPF) to solve the above problems. ARPF algorithm reduces the redundant accesses to the read only addresses of the global variables and static ones, increases the amount of instruction level parallelism of a program, and avoids the performance declines due to the increase in register pressure caused by register promotion. The algorithm has been implemented in the Loongson compiler for MIPS architecture. Experiments on SPEC CPU2000INT benchmarks are conducted to show that ARPF can improve the performance of all benchmarks by 1%-6%.

关键词： Benchmarking

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Echo state transfer learning for data correlation aware resource allocation in wireless virtual reality

arXiv

引用

arXiv 2017年

作者： Chen, Mingzhe Saad, Walid Yin, Changchuan Debbah, Mérouane Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China Wireless-VT Bradley Department of Electrical and Computer Engineering Virginia Tech BlacksburgVA United States Mathematical and Algorithmic Sciences Lab Huawei France R & D Paris France

In this paper, the problem of data correlation-aware resource management is studied for a network of wireless virtual reality (VR) users communicating over cloud-based small cell networks (SCNs). In the studied model, small base stations (SBSs) with limited computational resources act as VR control centers that collect the tracking information from VR users over the cellular uplink and send them to the VR users over the downlink. In such a setting, VR users may send or request correlated or similar data (panoramic images and tracking data). This potential spatial data correlation can be factored into the resource allocation problem to reduce the traffic load in both uplink and downlink. This VR resource allocation problem is formulated as a noncooperative game that allows jointly optimizing the computational and spectrum resources, while being cognizant of the data correlation. To solve this game, a transfer learning algorithm based on the machine learning framework of echo state networks (ESNs) is proposed. Unlike conventional reinforcement learning algorithms that must be executed each time the environment changes, the proposed algorithm can intelligently transfer information on the learned utility, across time, to rapidly adapt to environmental dynamics due to factors such as changes in the users' content or data correlation. Simulation results show that the proposed algorithm achieves up to 16.7% and 18.2% gains in terms of delay compared to the Q-learning with data correlation and Q-learning without data correlation. The results also show that the proposed algorithm has a faster convergence time than Q-learning and can guarantee low delays. Copyright © 2017, The Authors. All rights reserved.

关键词： Virtual reality

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Using Data-Level Parallelism to Accelerate Instruction -Level Redundancy

Using Data-Level Parallelism to Accelerate Instruction -Leve...

引用

World Automation Congress

作者： Yu Hu Zhong liang Chen Xiaowei Li Key Laboratory of Computer System and Architecture Institute of Computing Technology CAS Beijing 100190 China Department of Electrical and Computer Engineering Northeastern University Boston MA 02115 USA

ISBN: (纸本)9781467344975

Instruction-level redundancy is an effective scheme to reduce the susceptibility of microprocessors to soft errors, offering high error detection and recovery capability;however, it usually incurs significant performance degradation due to resource racing. Motivated by the fact that narrow-width operands are commonly seen in applications, we exploit data-level parallelism to accelerate instruction-level redundancy. For the instructions within sphere of replication (SoR) of data-level redundancy, normal and redundant versions of the narrow-width operand of the instruction are folded into one register to share the same functional unit during execution hence alleviating resource racing. The other instructions are all protected by instructionlevel redundancy. We run SPECint2000 benchmarks on a modified version of SimpleScalar simulator, and synthesize the extra hardware to evaluate area overhead of the proposed pipeline. Experimental results show that our acceleration scheme outperforms conventional instruction-level redundancy by 13% in IPC. Besides, the extra area overhead is negligible.

关键词： keywords Data-level redundancy Instruction-level redundancy Narrow-width value Sphere of replication

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Digital Over-the-Air Federated Learning in Multi-Antenna systems

arXiv

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arXiv 2023年

作者： Wang, Sihua Chen, Mingzhe Shen, Cong Yin, Changchuan Brinton, Christopher G. The Beijing Laboratory of Advanced Information Network The Beijing Key Laboratory of Network System Architecture and Convergence Beijing University of Posts and Telecommunications Beijing100876 China The Department of Electrical and Computer Engineering Institute for Data Science and Computing University of Miami Coral GablesFL33146 United States The Charles L. Brown Department of Electrical and Computer Engineering University of Virginia CharlottesvilleVA United States The School of Electrical and Computer Engineering Purdue University West LafayetteIN United States

In this paper, the performance optimization of federated learning (FL), when deployed over a realistic wireless multiple-input multiple-output (MIMO) communication system with digital modulation and over-the-air computation (AirComp) is studied. In particular, a MIMO system is considered in which edge devices transmit their local FL models (trained using their locally collected data) to a parameter server (PS) using beamforming to maximize the number of devices scheduled for transmission. The PS, acting as a central controller, generates a global FL model using the received local FL models and broadcasts it back to all devices. Due to the limited bandwidth in a wireless network, AirComp is adopted to enable efficient wireless data aggregation. However, fading of wireless channels can produce aggregate distortions in an AirComp-based FL scheme. To tackle this challenge, we propose a modified federated averaging (FedAvg) algorithm that combines digital modulation with AirComp to mitigate wireless fading while ensuring the communication efficiency. This is achieved by a joint transmit and receive beamforming design, which is formulated as an optimization problem to dynamically adjust the beamforming matrices based on current FL model parameters so as to minimize the transmitting error and ensure the FL performance. To achieve this goal, we first analytically characterize how the beamforming matrices affect the performance of the FedAvg in different iterations. Based on this relationship, an artificial neural network (ANN) is used to estimate the local FL models of all devices and adjust the beamforming matrices at the PS for future model transmission. The algorithmic advantages and improved performance of the proposed methodologies are demonstrated through extensive numerical experiments. Copyright © 2023, The Authors. All rights reserved.

关键词： Beamforming

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Design of a flip-flop circuit within digital logic analyzer based on FPGA

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Harbin Gongye Daxue Xuebao/Journal of Harbin Institute of Technology 2009年第SUPPL. 1期41卷 58-62页

作者： Xiao, Ling-Li Xu, Ning Han, Yin-He School of Computer Science and Technology Wuhan University Of Technology Wuhan 430070 China System Architecture Key Laboratory Institute of Computing Technology Chinese Academy of Sciences Beijing 100190 China

With the wide application of EDA technique, the period for the development of electronic products has been shortened. That implements the software of the hardware design and reduces the costs. Based on the analysis of the principle of digital logic analyzer circuit, this paper discusses the working principles of its flip-flop circuit module and the implementation method of FPGA, and presents the program design and emulation result of part circuits.

关键词： Field programmable gate arrays (FPGA)

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Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects

Codeword Selection for Crosstalk Avoidance and Error Correct...

引用

26th IEEE VLSI Test Symposium (VTS 2008)

作者： Ying Zhang Huawei Li Xiaowei Li Yu Hu Graduate School of Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

Crosstalk effects and soft errors on interconnects have been increasingly serious, which affects normal communication among cores. Therefore, it is desirable to design a reliable bus system without causing unacceptable performance reduction. In this paper, a new bus encoding method based on codeword selection is presented for enduring crosstalk-induced effects, which can avoid crosstalk and provide error correction as well. This method finds a subset from crosstalk avoidance code (CAC) to provide error correction. It can avoid crosstalk induced by late signal transition on checking bits in the previous methods. Extra wires for checking bus are never required in the proposed method. Experiment shows that the method reduces 6% wire overhead compared to the former methods. And it can also improve bus performance and reduce power dissipation.

关键词： Crosstalk Error correction codes Wires Delay Encoding Very large scale integration Power system interconnection Digital audio players Error correction Capacitance

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