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10th IEEE International Conference on computer Aided Design and computer Graphics(第十届CAO/Graphics国际会议)

作者： Dong Xu Hua Li Key Laboratory of Intelligent Information Processing Key Laboratory of Computer System and Architecture National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Academy of Sciences Graduate University of Chinese

In this paper,volume models are obtained from closed surface models by an accurate voxelization method which can handle the hidden cavities. This kind of 3D binary images is then converted to gray-level images by a fast Euclidean distance transform (EDT).Moment invariants (MIs) which are invariant shape descriptors under similarity transformations,are then computed based on the gray images. Applications in shape analysis area such as principal axis determination,skeleton and medial axis extraction,and shape retrieval can be carried out base on EDT and MIs.

关键词： Shape Euclidean distance Skeleton Principal component analysis Laboratories Image converters Data mining Computed tomography Clouds Iterative closest point algorithm

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Design of NIC Based on I/O Processor for Cluster Interconnect Network

Design of NIC Based on I/O Processor for Cluster Interconnec...

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International Conference on Networking, architecture, and Storage (NAS)

作者： Xiaojun Yang Dongdong Wu Ninghui Sun National Research Center for Intelligent Computing Systems Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

An effective interconnect network interface card (NIC) is critical to the achievement of a high-performance cluster system. An original NIC architecture based on the Intel IOP310 I/O processor chipset is presented in this paper. The NIC is a part of DCNet, which is the cluster interconnect network developed by NCIC. The I/O processor makes it powerful for the NIC to offload the processing of communication protocol from the host CPU. In the NIC architecture, the memory bus is extended to be a local bus for system peripheral interconnection, and a memory integrated network interface (MINI) is implemented and embedded. The testing results of DCNet show that the NIC obtains reasonable user-level communication performance, and prove that the NIC architecture, which based on I/O processor and the MINI approach, is feasible and effective to achieve the high performance.

关键词： computer architecture computer networks Network interfaces Supercomputers Bandwidth Intelligent systems Intelligent networks computer interfaces Power system interconnection Protocols

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Reliable and Energy Efficient Protocol for Wireless Sensor Network

Reliable and Energy Efficient Protocol for Wireless Sensor N...

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第十二届全国容错计算学术会议

作者： KAN Baoqiang CAI Li XU Yongjun College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer Sy College of Science Air Force Engineering UniversityXi'an 710052China Key Laboratory of Computer System and Architecture Institute of Computing TechnologyChinese Academy

Low-power design is one of the most important issues in wireless sensor networks (WSNs), while reliable information transmitting should be ensured as well. Transmitting power (TP) control is a simple method to make the power consumption down, but excessive interferences from potential adjacent operating links and communication reliability between nodes should be considered. In this paper, a reliable and energy efficient protocol is presented, which adopts adaptive rate control based on an optimal TP. A mathematical model considering average interference and network connectivity was used to predict the optimal TP. Then for the optimal TP, active nodes adaptively chose the data rate with the change of bit-error-rate(BER) performance. The efficiency of the new strategy was validated by mathematical analysis and simulations. Compared with 802.11 DCF which uses maximum unified TP and BASIC protocol, it is shown that the higher average throughput can achieve while the energy consumption per useful bit can be reduced according to the results.

关键词： wireless sensor networks reliable communication energy efficient optimal transmitting power adaptive link control

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Bug analysis and corresponding error models in real designs

Bug analysis and corresponding error models in real designs

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IEEE International High-Level Design Validation and Test Workshop

作者： Tao Lv Tong Xu Yang Zhao Huawei Li Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China Microprocessor Center Department of Computer Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China

This paper presents the item-missing error model. It stems from the analysis of real bugs that are collected in two market-oriented projects: (1) the AMBA interface of a general-purpose microprocessor IP core; (2) a wireless sensor network oriented embedded processor. The bugs are analyzed via code structure comparison, and it is found that item-missing errors merit attention. The test generation method for item-missing error model is proposed. Structural information obtained from this error model is helpful to reach a greater probability of bug detection than that in random-generation verification with only functional constraints. Finally, the proposed test method is applied in verification of our designs, and experimental results demonstrate the effectiveness of this method.

关键词： Error analysis computer bugs Microprocessors Circuit faults computer errors computer architecture Circuit testing Automatic test pattern generation Genetic mutations Laboratories

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The design-for-testability features of a general purpose microprocessor

The design-for-testability features of a general purpose mic...

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IEEE International Test Conference

作者： Da Wang Xiaoxin Fan Xiang Fu Hui Liu Ke Wen Rui Li Huawei Li Yu Hu Xiaowei Li Chinese Academy of Sciences Beijing China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy and Sciences Beijing China STMicroelectronics (Shanghai) Company Limited Shanghai China

This paper describes the design-for-testability (DFT) features and test challenges in a general purpose microprocessor design. An optimized DFT architecture with its implementation strategies are presented in detail. ... 详细信息

关键词： Microprocessors Clocks Design for testability Circuit testing Logic testing Circuit faults Manufacturing Power dissipation CMOS technology Phase locked loops

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Loop fusion conscious inline model

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第7期44卷 1265-1271页

作者： Zhou, Qian Feng, Xiaobing Zhang, Zhaoqing Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China

Optimization directed inlining is a good direction for inlining, but it does not consider the factor of the execution frequency and size of the function. Although a traditional inlining model considers the factor of execution frequency and size of the function, it does not consider the optimization after inlining. In this paper, a new inline model, loop fusion conscious inline model, is proposed to avoid these drawbacks of the inline model of the past. It considers both execution frequency and size and optimization. The inlining method which only considers loop fusion is implemented and is added into the ORC's original inline model. Then the new inline model is built and the model is tuned for high performance. In the experiment, some fact is found that temperature (execution frequency) isn't effective in some cases, and the reason is analyzed. Experiment result shows that the new model can greatly improve the performance of the compiler, and some SPEC CPU 2000 benchmark's peak performance can increase as high as 6%, and 1% on average.

关键词： Program compilers

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3-D projective moment invariants

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Journal of Information and Computational Science 2007年第2期4卷 821-828页

作者： Xu, Dong Li, Hua Key Laboratory of Intelligent Information Processing Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China National Research Center for Intelligent Computing Systems Institute of Computing Technology Chinese Acad. of Sci. Beijing 100080 China Graduate University Chinese Acad. of Sci. Beijing 100080 China

2-D projective moment invariants were firstly proposed by Suk and Flusser in [12]. We point out here that there is a useless projective moment invariant which is equivalent to zero in their paper. 3-D projective moment invariants are generated theoretically by investigating the property of signed volume of a tetrahedron. The main part is the selection of permutation invariant cores for multiple integrals to generate independent and nonzero 3-D projective moment invariants. We give the conclusion that projective moment invariants don't exist strictly speaking because of their convergence problem.

关键词： computer vision

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Cache adaptive write allocate policy

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第2期44卷 348-354页

作者： Huan, Dandan Li, Zusong Hu, Weiwu Liu, Zhiyong Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The bandwidth becomes the major bottleneck of the performance improvement for modern microprocessors. A cache adaptive write allocate policy that improves the bandwidth of microprocessor significantly is proposed by investigating cache store misses. The cache adaptive write allocate policy collects fully modified blocks in miss queue. Fully modified blocks are written to lower level memory based on non-write allocate policy which can switch to write allocate policy adaptively. Compared with other cache store miss policies, the cache adaptive write allocate policy avoids unnecessary memory traffic, reduces cache pollution and decreases load and store queue full rate without increasing hardware overhead. Experiment results indicate that on average 62.6% memory bandwidth in STREAM benchmarks is improved by utilizing the cache adaptive write allocate policy. The performance of SPEC CPU 2000 benchmarks is also improved efficiently. The average IPC speedup is 5.9%.

关键词： Microprocessor chips

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Physical-annotation-based power modeling and estimation method for processor

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Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of computer-Aided Design and computer Graphics 2007年第11期19卷 1471-1475页

作者： Huang, Kun Zhang, Ge Wang, Jun Zeng, Hongbo Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

The proposed method is focused on synthesis-based static circuits, and a power modeling library is developed for modeling processors by means of parametric RTL and physical annotation, and all kinds of processor modules are mapped into combinations of basic components. Those models are linked to an architectural simulator, running benchmarks to get power results. The power analysis of benchmark platforms proves to be effective and highly correlated, with an average 10% error and little speed penalty compared with the gate-level power analysis.

关键词： High performance processor Physical annotation Power estimation Power modeling

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Innovative architecture-level power estimation methodology for godson processor

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Jisuanji Yanjiu yu Fazhan/computer Research and Development 2007年第5期44卷 782-789页

作者： Huang, Kun Zhang, Longbing Hu, Weiwu Zhang, Ge Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing 100080 China Graduate University Chinese Academy of Sciences Beijing 100049 China

Now the research of computer architecture focuses on how to utilize the energy of CPU to attain high performance as much as possible. Obviously the architecture-level power estimation tool is important. Existing architecture-level power simulators only focus on full-custom dynamic circuits modeling, but ignores the power modeling of ASIC designs which are mainly composed of static circuits or standard cell libraries. So this paper is concerned with the implementation of a high performance and low power general purpose CPU, the Godson-2 processor, and analyzes the power characteristics of the CPU, and implements an architecture-level power estimation methodology which aims at the Godson-2 processor. This methodology takes the power modeling methodology of CMOS static circuits into account carefully, so it is better for the estimation of current high performance CPU architecture which is designed with ASIC methodology. Compared with the RTL power estimating method, this methodology has high speed and high flexibility and the accuracy is also very good. On the platform of Intel Xeon 2.4 GHz, the speed of this methodology is about 300 K instructions per second, which is 5000 times that of the RTL power estimating method with only little error penalty.

关键词： Microprocessor chips

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