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AdaptHM: A Fully Adaptive data Migration Strategy for Hybrid Memory systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2025年第3期44卷 923-936页

作者： Peng, Zhouxuan Feng, Dan Chen, Jianxi Hu, Jing Liu, Yachun Hu, Jinlei Zhang, Jintong Wan, Tianyu Chen, Zuoning Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology MoE of China Wuhan430074 China Chinese Academy of Engineering Beijing100088 China

data migration strategies (DMSs) improve the overall performance of hybrid memory systems by migrating frequently accessed (hot) data to faster memory. However, designing an efficient DMS is challenging since the key metrics of DMS - hot data selection, migration granularity, and migration frequency - are sensitive to access patterns of workloads. Most existing strategies focus on only one of these metrics and often overlook the crucial impact of access patterns, resulting in suboptimal performance and unnecessary migration traffic. In this article, we propose AdaptHM, a fully access-pattern-aware Adaptive DMS for Hybrid Memory systems. AdaptHM achieves adaptability on all three metrics through its unique multilevel data framework. First, AdaptHM adopts a group-level competition policy to select hot blocks, which responds faster to access patterns than threshold-based policies. Second, AdaptHM enables segment-level dynamic migration granularity by decoupling migration from remapping, which shows better-access pattern resilience than existing schemes with fixed-size global migration granularity. Third, AdaptHM adjusts the migration frequency at set-level by periodically assessing the migration benefit, avoiding unnecessary migrations. Experimental results demonstrate that AdaptHM improves the performance by an average of 12.78% and reduces energy consumption by up to 37.24% compared to the state-of-the-art scheme. © 1982-2012 IEEE.

关键词： Frequency modulation

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DRCTL: A Disorder-Resistant Computation Translation Layer Enhancing the Lifetime and Performance of Memristive CIM Architecture 57

DRCTL: A Disorder-Resistant Computation Translation Layer En...

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57th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2024

作者： Zhou, Heng Wu, Bing Cheng, Huan Liu, Jinpeng Lei, Taoming Feng, Dan Tong, Wei School of Computer Science and Technology Huazhong University of Science and Technology Ministry of Education of China Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology China

ISBN: (纸本)9798350350579

The memristive Computing-in-Memory (CIM) sys-Tem can efficiently accelerate matrix-vector multiplication (MVM) operations through in-situ computing. The data layout has a significant impact on the communication performance of CIM systems. Existing software-level communication opti-mizations aim to reduce communication distance by carefully designing static data layouts, while wear-leveling (WL) and error mitigation methods use dynamic scheduling to enhance system reliability, resulting in randomized data layouts and increased communication overhead. Besides, existing CIM compilers di-rectly map data to physical crossbars and generate instructions, which causes inconvenience for dynamic scheduling. To address these challenges of balancing communication performance and reliability while coordinating existing CIM compilers and dy-namic scheduling, we propose a disorder-resistant computation translation layer (DRCTL), which improves system lifetime and communication performance through co-optimization of data layout and dynamic scheduling. It consists of three parts: (1) We propose an address conversion method for dynamic scheduling, which updates the addresses in the instruction stream after dynamic scheduling, thereby avoiding recompilation. (2) Dynamic scheduling strategy for reliability improvement. We propose a hierarchical wear-leveling (HWL) strategy, which reduces communication by increasing scheduling granularity. (3) Communication optimization for dynamic scheduling. We propose data layout-Aware selective remapping (LASR), which helps dynamic scheduling methods improve communication lo-cality and reduce latency by exploiting data dependencies. The experiments demonstrate that HWL extends lifetime by 100.3-205.9 x compared to not using WL. Even with a slight lifetime decrease compared to the state-of-The-Art WL (TIWL), it still supports continuous neural network training for 7 years. After applying LASR to HWL, the number of execution cycles, energy consumption

关键词： Program compilers

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Parallelism or Fairness? How to Be Friendly for SSDs in Cloud Environments

Parallelism or Fairness? How to Be Friendly for SSDs in Clou...

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2024 IEEE International Conference on Cluster Computing, CLUSTER 2024

作者： Zhou, Yang Wang, Fang Shi, Zhan Feng, Dan Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Wuhan China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9798350358711

Modern SSDs achieve low latency and high throughput by utilizing multiple levels of SSD parallelism. Fairness is also a critical design consideration in cloud environments and has inspired great interest in recent years to study it. However, we find that excessive striving for SSD parallelism can inadvertently harm the SSD fairness due to the striped data layout. We observe from our experimental analysis that some common access patterns in cloud loads (e.g., high-intensity I/O) are not addressed by SSD parallelism, which can affect both SSD parallelism and fairness. In this paper, we analyze two address mapping policies with orthogonal characteristics from SSD parallelism and fairness perspectives. Based on extensive experiments and observations, we schedule a hybrid address mapping policy to achieve fairness of SSDs in cloud environments by distinguishing different I/O access modes and cold/hot data, while ensuring SSD performance. Experimental results on the latest block-level I/O traces show that our approach significantly improves performance and fairness by up to 77.3% and 62.8%, respectively, over the previous schemes with negligible cost. Meanwhile, it can also reduce the write amplification by 23.5% to 33.5%. © 2024 IEEE.

关键词： Cloud platforms

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An efficient memory data organization strategy for application-characteristic graph processing

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Frontiers of Computer Science 2022年第1期16卷 191-193页

作者： Peng FANG Fang WANG Zhan SHI Dan FENG Qianxu YI Xianghao XU Yongxuan ZHANG Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage SystemEngineering Research Center of data storage systems and TechnologyMinistry of Education of ChinaSchool of Computer Science and TechnologyHuazhong University of Science and TechnologyWuhan430074China

1 Introduction Graph processing has received significant attention for its ability to cope with large-scale and complex unstructured data in the ***,most of the graph processing applications exhibit an irregular memor... 详细信息

关键词： application processing pattern

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TERMS: Task management policies to achieve high performance for mixed workloads using surplus resources

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Journal of Parallel and Distributed Computing 2022年第0期170卷 74-85页

作者： Yu, Jinyu Tong, Wei Lv, Pengze Feng, Dan Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology School of Computer Science and Technology Huazhong University of Science and Technology Ministry of Education of China Hubei Wuhan China

Resource contentions and performance interferences can lead to workload performance degradation in mixed-workload deployment clusters. Previous work guarantees the resource requirements of latency-sensitive tasks and reduces performance losses to batch jobs by reclaiming surplus resources from over-provisioned tasks. While the fragmentation of resources leads to a mismatch between provisioned resources and task requirements, resulting in high operation overheads and losses of task fairness. This paper proposes TERMS, the task management policies based on task relevance, resource distribution, and task fairness to achieve efficient and low-cost task management. TERMS mainly includes three types of management policies. The task scheduling policy can schedule new tasks according to task relevance. Task selection strategies select tasks for resource provisioning and task resumption based on resource requirements and task fairness. If necessary, the node selection strategy can be used to choose befitting target nodes based on task relevance and node resource information for task migration when eliminating straggler tasks. Evaluation results show that TERMS can further improve the performance of latency-sensitive services and batch jobs, reduce management overheads, and avoid operation failures. © 2022 Elsevier Inc.

关键词： Scheduling

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Seastar: A Cache-Efficient and Load-Balanced key-Value Store on Disaggregated Memory

Seastar: A Cache-Efficient and Load-Balanced Key-Value Store...

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2024 IEEE International Conference on Cluster Computing, CLUSTER 2024

作者： Du, Jingwen Wang, Fang Feng, Dan Zeng, Dexin Yi, Sheng Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System China School of Computer Science and Technology Huazhong University of Science and Technology China Shenzhen Huazhong University of Science and Technology Research Institute China

ISBN: (纸本)9798350358711

In modern datacenters, memory disaggregation un-packs monolithic servers to build independent network-connected compute and memory pools, greatly improving resource uti-lization. Existing memory-disaggregated key-value stores adopt ownership sharing or ownership partitioning for request scheduling and they all show poor performance and scalability. The former generates multiple cache misses and multiple network round trips due to poor cache locality, while the latter fails to fully use resources on all Compute Nodes (CNs) due to load imbalance. In this paper, we propose Seastar, a fast and scalable key-value store that achieves high cache locality as well as load balancing. To enable high concurrency and ensure linearizability, Seastar exploits a self-verification version chain to provide out-of-place atomic updates and ensure consistent reads. To improve cache locality, Seastar leverages a pair-based ownership assigning scheme to assign the processing permission of requests corre-sponding to each key to a CN pair through two independent hash functions. To ensure load balancing among CNs, Seastar proposes a decentralized power-of-two-choices routing scheme to route the requests to the less-loaded CNs in CN pairs for handling. Experimental results demonstrate that Seastar improves the throughput by up to 6.7x and significantly reduces the latency compared with state-of-the-art memory-disaggregated key-value stores. © 2024 IEEE.

关键词： Scalability

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Scavenger: Better Space-Time Trade-Offs for key-Value Separated LSM-trees 40

Scavenger: Better Space-Time Trade-Offs for Key-Value Separa...

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40th IEEE International Conference on data Engineering, ICDE 2024

作者： Zhang, Jianshun Wang, Fang Qiu, Sheng Wang, Yi Ou, Jiaxin Huang, Junxun Li, Baoquan Fang, Peng Feng, Dan School of Computer Science and Technology Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China China Shenzhen Huazhong University of Science and Technology Research Institute China Bytefrance Inc.

ISBN: (纸本)9798350317152

key-Value Stores (KVS) implemented with log-structured merge-tree (LSM-tree) have gained widespread ac-ceptance in storage systems. Nonetheless, a significant challenge arises in the form of high write amplification due to the compaction process. While KV-separated LSM-trees successfully tackle this issue, they also bring about substantial space am-plification problems, a concern that cannot be overlooked in cost-sensitive scenarios. Garbage collection (GC) holds significant promise for space amplification reduction, yet existing GC strategies often fall short in optimization performance, lacking thorough consideration of workload characteristics. Additionally, current KV-separated LSM-trees also ignore the adverse effect of the space amplification in the index LSM-tree. In this paper, we systematically analyze the sources of space amplification of KV-separated LSM-trees and introduce Scavenger, which achieves a better trade-off between performance and space amplification. Scavenger initially proposes an I/O-efficient garbage collection scheme to reduce I/O overhead and incorporates a space-aware compaction strategy based on compensated size to minimize the space amplification of index LSM-trees. Extensive experiments show that Scavenger significantly improves write performance and achieves lower space amplification than other KV-separated LSM-trees (including BlobDB, Titan, and TerarkDB). © 2024 IEEE.

关键词： Economic and social effects

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CMD: A Cache-Assisted GPU Memory Deduplication Architecture

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IEEE Transactions on Computer-Aided Design of Integrated Circuits and systems 2025年

作者： Zhao, Wei Feng, Dan Tong, Wei Wei, Xueliang Wu, Bing Ministry of Education of China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of data storage systems and Technology China

Massive off-chip accesses in GPUs are the main performance bottleneck. We find that many writes are duplicate, and the duplication can be inter-dup and intra-dup. While inter-dup means different memory blocks are identical, and intra-dup means all the 4B elements in a line are the same. In this work, we propose a cache-assisted GPU memory deduplication architecture named CMD to reduce the off-chip accesses via utilizing the data duplication in GPU applications. CMD includes three key design contributions which aim to reduce the three kinds of accesses: (1) A novel GPU memory deduplication architecture that removes the intra-dup and inter-dup lines. We design several techniques to manage duplicate blocks, reducing massive off-chip writes. (2) We propose a cache-assisted read scheme to reduce the reads to duplicate data. When an L2 cache miss wants to read the duplicate block, if the reference block has been fetched to L2 and it is clean, we can copy it to the L2 missed block without accessing off-chip DRAM. As for the reads to intra-dup data, CMD uses the on-chip metadata cache to get the data. (3) When a cache line is evicted, the clean sectors in the line are invalidated while the dirty sectors are written back. However, most read-only victims are re-referenced from DRAM more than twice. Therefore, we add a full-associate FIFO to accommodate the read-only (it is also clean) victims to reduce the re-reference counts. Experiments show that CMD can decrease the off-chip accesses by 31.01%, reduce the energy by 32.78% and improve performance by 42.53%. Besides, CMD can improve the performance of memory-intensive workloads by 57.56%. © 2025 IEEE.

关键词： Cache memory

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A Read Latency Variation Aware Independent Read Scheme for QLC SSDs

A Read Latency Variation Aware Independent Read Scheme for Q...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Dong Huang Dan Feng Qiankun Liu Bo Ding Wei Zhao Xueliang Wei Wei Tong Key Laboratory of Information Storage System Engineering Research Center for Data System and Technology Ministry of Education Wuhan National Laborotory of Optoelectronics Huazhong University of Science and Technology

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

QLC flash-based SSDs has attracted growing interest and is expected to fit in read-intensive scenarios owing to its higher cost-effectiveness and shorter write endurance compared with the Triple-Level Cell (TLC) SSDs. Recently, new commands supporting independent reads such as Single Operation Multiple Locations (SOML) and Independent multi-plane (IMP) read are proposed to improve read performance. Unfortuantely, while independent read exhibits a significant performance improvement, we show in this paper that the exisiting approach fails to fully exploit its potential due to the larger read latency variation and more planes per die for current SSD architecture. Through a set of experiments, we demonstrate that the lack of a read latency variation aware machanism leads to low performance of independent read among a wide variety of workloads. To alleviate this issue, we propose LITA, which key idea is to combine read transactions with similar latency into one command. LITA includes (1) LIT, a latency variation aware transaction combination, (2) and TASAP, a latency variation aware transaction completion service. The experimental results show LITA can reduce read latency by 20.4% and 9.6% on average for 4-planes QLC SSDs under IMP and SOML, respectively.

关键词： Microprocessors Computer architecture

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CorcPUM: Efficient Processing Using Cross-Point Memory via Cooperative Row-Column Access Pipelining and Adaptive Timing Optimization in Subarrays 23

CorcPUM: Efficient Processing Using Cross-Point Memory via C...

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Proceedings of the 60th Annual ACM/IEEE Design Automation Conference

作者： Chengning Wang Dan Feng Wei Tong Jingning Liu Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China (School of Computer Science and Technology Huazhong University of Science and Technology) Wuhan China

ISBN: (纸本)9798350323481

Emerging cross-point memory can in-situ perform vector-matrix multiplication (VMM) for energy-efficient scientific computation. However, parasitic-capacitance-induced row charging and discharging latency is a major performance bottleneck of subarray VMM. We propose a memory-timing-compliant bulk VMM processing-using-memory design with row access and column access co-optimization from rethinking of read access commands and μ-op timing. We propose row-level-parallelism-adaptive timing termination mechanism to reduce tail latency of tRCD and tRP by exploiting row nonlinear charging and bulk-interleaved row-column-cooperative VMM access mechanism to reduce tRAS and overlap CL without increasing column ADC precision. Evaluations show that our design can achieve 5.03× performance speedup compared with an aggressive baseline.

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