检索结果-内蒙古大学图书馆

International Conference on Networking, Architecture, and storage (NAS)

作者： Zhihu Tan Changsheng Xie Jiguang Wan Key Laboratory of Data Storage System Ministry of Education Huazhong University of Science and Technology Wuhan Hubei China Wuhan National Laboratory of Optoelectronics Wuhan Hubei China

When RAID volume is newly created, the data in RAID is then initialized. The process formats the RAID volume to clear any previously data and initialize redundancy information. This paper investigates others' initialization methods, and proposes a new initialization method. It makes RAID initialization and I/O request processing parallel, and reduces initialization time efficiently. Testing results reveals a moderately successful performance improvement.

关键词： Laboratories Disk drives Detectors Costs Random access memory data storage systems Educational technology Testing Process design Writing

来源：评论

学校读者我要写书评

暂无评论

ReRAM Crossbar-Based Analog Computing Architecture for Naive Bayesian Engine

ReRAM Crossbar-Based Analog Computing Architecture for Naive...

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Bing Wu Dan Feng Wei Tong Jingning Liu Chengning Wang Wei Zhao Mengye Peng Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology (School of Computer Science and Technology Huazhong University of Science and Technology) Ministry of Education of China

Recent advances in Resistive RAM (ReRAM) have explored the in-situ Matrix-Vector Multiplication (MVM) ability of crossbar arrays to achieve high energy-efficiency Process-In-Memory (PIM) architectures for Convolutional Neural Network (CNN), image processing, and so on. However, the existing ReRAM-based PIM architectures suffer from considerable additional auxiliary logic and device variations. In this work, we propose a novel analog computing architecture NB Engine for classification by implementing Naive Bayesian (NB) algorithm on ReRAM crossbar arrays. The two key steps of the NB algorithm, that is, probability calculation and electing the class that has the highest probability, are elaborately accomplished in our architecture. The ReRAM arrays are both used as storage and computation components. We store the pre-calculated prior probabilities and conditional probabilities of every class in crossbar arrays. Then the probability calculation step is completed in parallel through the MVM operation of the array. In general, the election step is a multiple-comparison procedure and is normally implemented by a comparison tree. Here, we reuse the max pooling module in a conventional CNN PIM architecture to realize a compatible comparison logic. However, neither of the two designs can avoid the overhead of costly high bit-precision Analog-to-Digital Converters (ADCs). So we introduce a novel analog parallel comparison design which does not need any ADCs or other computing logic with better energy-saving and area-efficiency. Our proposed NB Engine is tested by 11 various datasets. The influence of several non-ideal device properties is discussed and the NB Engine exhibits great tolerance to these variations. The experiment results show that our design offers a runtime speedup up to 2289.6x compared with the software-implemented NB classifier with negligible accuracy loss. In addition, the NB Engine saves 96.2% energy consumption and 45.2% array area compared with the CNN P

关键词：

来源：评论

学校读者我要写书评

暂无评论

MorLog: Morphable Hardware Logging for Atomic Persistence in Non-Volatile Main Memory

MorLog: Morphable Hardware Logging for Atomic Persistence in...

引用

Annual International Symposium on Computer Architecture, ISCA

作者： Xueliang Wei Dan Feng Wei Tong Jingning Liu Liuqing Ye Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology (School of Computer Science and Technology Huazhong University of Science and Technology) Ministry of Education of China

ISBN: (数字)9781728146614

ISBN: (纸本)9781728146621

Byte-addressable non-volatile memory (NVM) is emerging as an alternative for main memory. Non-volatile main memory (NVMM) systems are required to support atomic persistence and deal with the high overhead of programming NVM cells. To this end, recent studies propose hardware logging and data encoding designs for NVMM systems. However, prior hardware logging designs incur either extra ordering constraints or redundant log data. Moreover, existing data encoding designs are unaware of the characteristics of log data, resulting in writing unnecessary log *** this paper, we propose a morphable hardware logging design (MorLog) that only logs the data necessary for recovery and dynamically selects encoding methods with least write overhead. We observe that (1) only the oldest undo and the newest redo data in each transaction are necessary for recovery, and (2) the log data for clean bits are clean. The first motivates our morphable logging mechanism. This mechanism logs both undo and redo data for the first update to the data in a transaction, and then logs only redo data. Undo data are eagerly written to NVMM to ensure atomicity, while redo data are buffered in a volatile log buffer and L1 caches to write only the newest redo data to NVMM. The second motivates our selective log data encoding mechanism. This mechanism simultaneously encodes log data with different methods, and writes the encoded log data with the least write cost to NVMM. We devise a differential log data compression method to exploit the characteristics of log data. This method directly discards clean bits from log data and compresses remained dirty bits. Our evaluation shows that MorLog improves performance by 72.5%, reduces NVMM write traffic by 41.1%, and decreases NVMM write energy by 49.9% compared with the state-of-the-art design.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Fuzzy Reliability Analysis of Two-Disk Failure-Tolerant Disk Arrays

Fuzzy Reliability Analysis of Two-Disk Failure-Tolerant Disk...

引用

International Conference on Convergence Information Technology

作者： MingHua Jiang Jingli Zhou Ming Hu YiXiang Ding College of Computer Science &Technology Wuhan University of Science and Engineering Wuhan China Ministry of Education Key Laboratory of Data Storage System Wuhan China

ISBN: (纸本)9781424431779

This paper presents a data placement of a two-disk failure-tolerant disk arrays system, a code-mixing solution RAID5x with XOR-based code and mirror for disk arrays to improve performance of accessing storage system with high reliability. RAID5x is not only just higher in storage efficiency than other code-mixing solutions of the same type, but also it has the higher accessing performance over them and XOR-based code solutions, and then analyzed the reliability of this system by combination of fuzzy logic and Markov modeling. This reliability method is a technique for analyzing fault tolerant designs under considerable uncertainty, such as is seen in compilations of component failure rates, the presented model provides the estimation of the lower and upper boundary of a two-disk failure-tolerant disk array system with a single run of the model.

关键词： Failure analysis Redundancy Fuzzy logic Reliability engineering Performance analysis Information technology Information analysis Educational institutions Computer science Laboratories

来源：评论

学校读者我要写书评

暂无评论

DRCTL: A Disorder-Resistant Computation Translation Layer Enhancing the Lifetime and Performance of Memristive CIM Architecture

DRCTL: A Disorder-Resistant Computation Translation Layer En...

引用

IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Heng Zhou Bing Wu Huan Cheng Jinpeng Liu Taoming Lei Dan Feng Wei Tong Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology School of Computer Science and Technology Huazhong University of Science and Technology Ministry of Education of China

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

The memristive Computing-in-Memory (CIM) sys-tem can efficiently accelerate matrix-vector multiplication (MVM) operations through in-situ computing. The data layout has a significant impact on the communication performance of CIM systems. Existing software-level communication opti-mizations aim to reduce communication distance by carefully designing static data layouts, while wear-leveling (WL) and error mitigation methods use dynamic scheduling to enhance system reliability, resulting in randomized data layouts and increased communication overhead. Besides, existing CIM compilers di-rectly map data to physical crossbars and generate instructions, which causes inconvenience for dynamic scheduling. To address these challenges of balancing communication performance and reliability while coordinating existing CIM compilers and dy-namic scheduling, we propose a disorder-resistant computation translation layer (DRCTL), which improves system lifetime and communication performance through co-optimization of data layout and dynamic scheduling. It consists of three parts: (1) We propose an address conversion method for dynamic scheduling, which updates the addresses in the instruction stream after dynamic scheduling, thereby avoiding recompilation. (2) Dynamic scheduling strategy for reliability improvement. We propose a hierarchical wear-leveling (HWL) strategy, which reduces communication by increasing scheduling granularity. (3) Communication optimization for dynamic scheduling. We propose data layout-aware selective remapping (LASR), which helps dynamic scheduling methods improve communication lo-cality and reduce latency by exploiting data dependencies. The experiments demonstrate that HWL extends lifetime by 100.3-205.9 x compared to not using WL. Even with a slight lifetime decrease compared to the state-of-the-art WL (TIWL), it still supports continuous neural network training for 7 years. After applying LASR to HWL, the number of execution cycles, energy consumption

关键词： Training Energy consumption Processor scheduling Layout Dynamic scheduling In-memory computing Common Information Model (computing) system-on-chip Reliability Optimization

来源：评论

学校读者我要写书评

暂无评论

The system Design and Performance Analysis of WiMAX Base Station MAC Based on Intel Network Processor

The System Design and Performance Analysis of WiMAX Base Sta...

引用

International Conference on Networking, Architecture, and storage (NAS)

作者： Ming Wu Changsheng Xie Qingdong Wang Key Laboratory of Data Storage System Chinese Ministry of Education Computer School Huazhong University of Science슠and슠Technology Wuhan Hubei China

This paper provides WiMAX BS (base station) MAC system design and performance analysis based on Intel IXP2350, which includes MAC design key issues discussion, base station usage model and architecture, MAC hardware and software high level design with performance analysis. Especially, the WiMAX base station is user-specific, and WiMAX MAC software is one of the most important base station components, so we discuss in details about MAC data plane software design and performance pre-analysis based on IXP2350 micro engines. Current hardware GE forwarding test and data plane software pre-analysis shows that the design scheme can meet system performance requirement.

关键词： system analysis and design Performance analysis WiMAX Base stations Software performance Hardware Software design Computer architecture Engines Software testing

来源：评论

学校读者我要写书评

暂无评论

Segment-Level Cross-Modal Knowledge Transfer for Speech Sentiment Analysis 4

Segment-Level Cross-Modal Knowledge Transfer for Speech Sent...

引用

4th IEEE International Conference on Computer and Communication Engineering Technology, CCET 2021

作者： Zhang, Sheng Chen, Jincai Li, Minglei Li, Taisong Lu, Ping Wang, Zhu Huazhong University of Science and Technology Wuhan National Laboratory for Optoelectronics Wuhan430074 China Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China Wuhan430074 China School of Computer Science and Technology Huazhong University of Science and Technology Wuhan430074 China Huawei Cloud Bu Shenzhen518129 China Huawei Technology Co. Ltd. Shenzhen518129 China

ISBN: (纸本)9781665438902

Speech sentiments are inherently dynamic. However, most of the existing methods for speech sentiment analysis follow the paradigm: one single hard label for an entire utterance, which results in that segment-level fine-grained sentiment information is unavailable and sentiment dynamics can not be considered. In addition, due to the ambiguity of sentiments, it is difficult and time-consuming to annotate an utterance at the segment level. In this work, to alleviate the above issues, we propose to use sentiment profiles (SPs), which give a time series of the segment-level soft labels to capture the fine-grained sentiment cues across an utterance. To obtain a large number of labeled data with segment-level annotations, we propose a cross-modal knowledge transfer method at the segment level to transfer facial expression knowledge from images to audio segments. Further, we propose the sentiment profile refinery (SPR) to iteratively update sentiment profiles to improve the accuracy of SPs and overcome the noise problem in the cross-modal knowledge transfer method. Our experiments on the CH-SIMS dataset with the iQIYI-VID dataset as unlabeled data show that our method can effectively exploit additional unlabeled audio-visual data and achieve state-of-the-art performance. © 2021 IEEE.

关键词： Sentiment analysis

来源：评论

学校读者我要写书评

暂无评论

An Analytical Model for Scheduling Policies in storage Networks

An Analytical Model for Scheduling Policies in Storage Netwo...

引用

International Workshop on Networking, Architecture, and storages (IWNAS)

作者： Diqing Hu Qiang Cao Changsheng Xie Key Laboratory of Data Storage System Chinese Ministry of EducationComputer School Huazhong University of Science슠and슠Technology Wuhan Hubei China

The I/O routine in network storage has longer transferring time and overhead than local I/O. To well make use of the storage network bandwidth and meet demand of concurrent I/O requests, we need to find the appropriate schedule policy for I/O requests at the level of the network. The focus in the paper is on how to schedule concurrent I/O data transferring in share storage network, and to improve performance such as the response time affected by scheduling method. Our objective is to analysis the response time of concurrent requests as function their schedule order such as the sequenced, parallel and hybrid policies. We then verify our results by both the analytical method and experiment

关键词： Analytical models Intelligent networks Delay TCPIP storage area networks Ethernet networks Linux Sockets Processor scheduling Laboratories

来源：评论

学校读者我要写书评

暂无评论

CMD: A Cache-assisted GPU Memory Deduplication Architecture

arXiv

引用

arXiv 2024年

作者： Zhao, Wei Feng, Dan Tong, Wei Wei, Xueliang Wu, Bing The Wuhan National Laboratory for Optoelectronics Key Laboratory of Information Storage System Engineering Research Center of Data Storage Systems and Technology Ministry of Education of China School of Computer Science and Technology Huazhong University of Science and Technology China

Massive off-chip accesses in GPUs are the main performance bottleneck, and we divided these accesses into three types: (1) Write, (2) data-Read, and (3) Read-Only. Besides, We find that many writes are duplicate, and the duplication can be inter-dup and intra-dup. While inter-dup means different memory blocks are identical, and intra-dup means all the 4B elements in a line are the same. In this work, we propose a cache-assisted GPU memory deduplication architecture named CMD to reduce the off-chip accesses via utilizing the data duplication in GPU applications. CMD includes three key design contributions which aim to reduce the three kinds of accesses: (1) A novel GPU memory deduplication architecture that removes the inter-dup and inter-dup lines. As for the inter-dup detection, we reduce the extra read requests caused by the traditional read-verify hash process. Besides, we design several techniques to manage duplicate blocks. (2) We propose a cache-assisted read scheme to reduce the reads to duplicate data. When an L2 cache miss wants to read the duplicate block, if the reference block has been fetched to L2 and it is clean, we can copy it to the L2 missed block without accessing off-chip DRAM. As for the reads to intra-dup data, CMD uses the on-chip metadata cache to get the data. (3) When a cache line is evicted, the clean sectors in the line are invalidated while the dirty sectors are written back. However, most read-only victims are re-referenced from DRAM more than twice. Therefore, we add a full-associate FIFO to accommodate the read-only (it is also clean) victims to reduce the re-reference counts. Experiments show that CMD can decrease the off-chip accesses by 31.01%, reduce the energy by 32.78% and improve performance by 37.79%. Besides, CMD can improve the performance of memory-intensive workloads by 50.18%. © 2024, CC BY-NC-ND.

关键词： Cache memory

来源：评论

学校读者我要写书评

暂无评论

Design and Implementation of IP-SAN Based on Third Party Transfer Protocols

Design and Implementation of IP-SAN Based on Third Party Tra...

引用

ISECS International Colloquium on Computing, Communication, Control, and Management, CCCM

作者： MingHua Jiang Ming Hu Jingli Zhou Tao Peng College of Computer Science Wuhan University of Science and Engineering Wuhan China Key Laboratory of Data Storage System Huazhong University of Science and Technology Wuhan China

The IP-SAN based on third party transfer protocols comprises host(s), controller(s) and stores by extending the SCSI-3 transport layer to support distribution application. In the implemented architecture data may be sent directly between host and stores, passing all commands through the controller retains simplicity, relieving the controller communication bottleneck. A prototype IP-SAN using Ethernet and Linux OS with the system implemented in the iSCSI transport layer protocol and in the controller's SCSI application layer, has been constructed. The theoretical analyses indicated that the factors affecting the iSCSI-based storage system including network performance, CRC computation in iSCSI protocol and the performance of the server. The performance test proves that the analysis is right.

关键词： Protocols storage area networks Servers Bandwidth IP networks Ethernet networks Performance evaluation

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：