In many fields of engineering and science, it is necessary to solve nonlinear equation systems (NESs). When using multiobjective optimization to solve NESs, there are two problems: 1) how to transform an NES into a mu...
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In order to address the issues of real-time performance and the low dependency between feature channels in fabric defect detection networks, this paper proposes the ESE-YOLOv5 network based on YOLOv5. Firstly, to addr...
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Emotion Detection in Conversation (EDC) has been implemented in numerous domains and is under increasing attention. The EDC task is highly challenging due to the need to incorporate both the context of the utterance a...
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In this paper, a third-order canonical circuit with a memristor is investigated. Unlike the conventional circuit systems, it has an equilibrium set, whose stability is affected by the initial state of the memristor. T...
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This paper proposed a H∞ based controller design method for MIMO system. We use the bound real lemma to design the controller when the reference model is given. The BMI (Bi-linear Matrix Inequality) problem is turned...
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This study aims to investigate containment control of linear multi-agent systems with input saturation on switching topologies. For such a multi-agent system, both state feedback and output feedback containment contro...
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This study investigates containment control of multi-agent systems with input saturation and multiple leaders on directed networks. Both state feedback and output feedback containment control protocols are designed vi...
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This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding (BPC) in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of co...
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This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding (BPC) in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel & pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture (PA) was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture (HA) was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an NxN code-block could be completed in approximate N2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.
Current protein nuclear localization assays encounter multiple challenges that underscore the constraints of conventional biochemical assays and sequence-based procedures. This paper highlights the emerging interest i...
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In the fields of information security, the application of random numbers is becoming more and more widespread. True random numbers (TRNs) tend to have better randomness and unpredictability than pseudo random numbers ...
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