The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only g...
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The quantization noise leakage of the first stage in a MASH21 sigma-delta modulator is analyzed. The results show that the finite DC gain of the opamp is the main reason for noise leakage, and finite GBW and SR only generate harmonic distortion. The relationship between DC gain and leakage is modeled and conclusions on design criteria are reached. As an example, a MASH21 modulator for a digital audio application is realized. This modulator, fabricated in an 0.18 μm mixed signal process, achieves an SNDR of 91 dB with 1.8 V supply, which verifies the analysis and design criteria.
This paper introduces a new method for SC sigma-delta modulator *** studies the integrator's different equivalent circuits in the integrating and sampling *** model uses the OP-AMP input pair's tail current(I_0) a...
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This paper introduces a new method for SC sigma-delta modulator *** studies the integrator's different equivalent circuits in the integrating and sampling *** model uses the OP-AMP input pair's tail current(I_0) and overdrive voltage(v_(on)) as *** modulator's static and dynamic errors are analyzed.A group of optimized I0 and von for maximum SNR and power x area ratio can be obtained through this *** examples, a MASH21 modulator for digital audio and a second order modulator for RFID baseband are implemented and tested, and they can achieve 91 dB and 72 dB respectively,which verifies the modeling and design criteria.
This article was originally published online on 13 July 2012 with an error in author Junsheng Cao’s name. The article was correct as it appeared in the printed
This article was originally published online on 13 July 2012 with an error in author Junsheng Cao’s name. The article was correct as it appeared in the printed
This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The ch...
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ISBN:
(纸本)9781424467372
This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.
Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to l...
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Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to l...
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Currently the ASIC applications such as multimedia processing require shorter time-to-market and higher performance. Furthermore, with the IC manufacturing technology developing continually, from transistor level to logic gate level, the size of standard cells in digital circuits is increasing correspondingly. New methodology should be proposed to meet the need for shorter time-to-market IC industry, and the requirement of advanced IC manufacturing technology. This paper proposed the concept and principle of operator design methodology, then focused on the entropy coding application by the reconfigurable operator and finally gave the synthesis data. The results show that compared with the hardware design at the same cost of resources, this methodology can obtain hardware of suitable performance with regular structure. What is more, it can improve the design speed efficiently.
This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The ch...
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This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5 v to 5.0 v with 0.1 v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5 μm mixed signal process, the die area is 0.24mm 2 , and the quiescent current is only 3 uA.
For the popular DIV page layout in Web Pages, this paper presents a method based on the position of DIV to extract main text from the body of Web pages by reconstructing, remaining atomic DIV and analyzing DIV positio...
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ISBN:
(纸本)9781424455850
For the popular DIV page layout in Web Pages, this paper presents a method based on the position of DIV to extract main text from the body of Web pages by reconstructing, remaining atomic DIV and analyzing DIV position. Experiments showed that the accuracy rate of extraction can reach more than 90%, with a high versatility and accuracy.
The detector response characteristics of the field effect MOS transistor (MOSFET) to modulated terahertz radiation signal are studied in details in this paper by a numerical simulation method developed from the basic ...
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A numerical method is proposed to simulate the corresponding terahertz photoresponse which is induced by radiations between source-and-gate and gate-and-drain electrodes in field effect transistors. Simulations illust...
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