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2012 IEEE 11th International Conference on Solid-State and Integrated circuit Technology, ICSICT 2012

作者： Chen, Meng Lu, Wengao Wang, Guannan Fang, Ran Zhang, Yacong Chen, Zhongjian Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781467324724

This paper presents a Switched-Capacitor Single-ended to Differential (SC-STD) stage for A/D conversion of an Infrared Focal Plane Array (IRFPA) Readout Integration circuit(ROIC). The SC-STD stage converts the output of the Capacitive Trans-Impedance Amplifier (CTIA) into differential signals, which can be used as the input of the subsequent A/D conversion. A novel Switched-Capacitor Common-Mode Feedback (SC-CMFB) technique with only two capacitors and single phase clock is proposed. Performances of the SC-STD stage are verified by a 14-bit column-paralleled Successive-Approximation A/D converter which is fabricated in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The THD of the SC-STD circuit is up to -94dB at a 1V Vpp input of 1.009 KHz. © 2012 IEEE.

关键词： Clocks

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Effect of Mo capping layers thickness on the perpendicular magnetic anisotropy in MgO/CoFeB based top magnetic tunnel junction structure

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Chinese Physics B 2016年第11期25卷 558-562页

作者：刘毅朱开贵钟汇才朱正勇于涛马苏德 School of Physics and Nuclear Energy Engineering Beihang University Key Laboratory of Micro-nano Measurement-Manipulation and Physics Ministry of Education Beihang University Integrated Circuit Advanced Process Center Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences

A detailed study of the magnetic characterizations of the top structure MgO/CoFeB/Mo is *** samples show strong perpendicular magnetic anisotropy（PMA） when the thickness of CoFeB is 0.9 nm and 1.1 *** saturation magnetic moment and interface anisotropy constant are 1566 emu/cm3 and 3.75 erg/cm2,*** magnetic dead layer（MDL） is about 0.23 nm in this ***,strong capping layer thickness dependence is also *** strong PMA of 1.1 nm CoFeB only exists in a Mo cap layer thickness window of 1.2-2 *** maintain PMA,the metal layer could not be too thin or thick in these *** oxidation and diffusion of the metal capping layer should be respectively responsibility for the degradation of PMA in these thin or thick metal capping layer samples.

关键词： anisotropy perpendicular junction annealing annealed thick saturation multilayer responsibility boron

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Effects of MgO Thickness and Roughness on Perpendicular Magnetic Anisotropy in MgO/CoFeB/Ta Multilayers

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Chinese Physics Letters 2016年第10期33卷 128-131页

作者：刘毅于涛朱正勇钟汇才朱开贵 School of Physics and Nuclear Energy Engineering Beihang University Key Laboratory of Microelectronic Devices & Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences Integrated Circuit Advanced Process Center Institute of MicroelectronicsChinese Academy of Sciences Key Laboratory of Micro-nano Measurement-Manipulation and Physics(Ministry of Education) Beihang University

The dependence of perpendicular magnetic anisotropy （PMA） on the barrier layer MgO thickness in MgO/CoFeB /Ta multilayers is investigated. The results show that the strongest PMA occurs in a small window of about 2 4nm with the increase of MgO thickness from 1-1Onto. The crystalline degree of MgO and the change of interatomic distance along the out-of-plane direction may be the main reasons for the change of PMA in these multilayers. Moreover, the roughnesses of 2- and 4-nm-thick MgO samples are 3.163 and 1.8 nm, respectively, and both the samples show PMA. These results could be used to tune the magnetic characteristic of the ultra thin CoFeB film for future applications in perpendicular magnetic devices.

关键词： PMA MgO of Effects of MgO Thickness and Roughness on Perpendicular Magnetic Anisotropy in MgO/CoFeB/Ta Multilayers in nm Ta on

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An Efficient Approach to Improve PSRR Performance of Kuijk BGR Topology

An Efficient Approach to Improve PSRR Performance of Kuijk B...

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology(第十届固态和集成电路技术国际会议 ICSICT-2010)

作者： Hui Nie Lijiu Ji Zhongjian Chen Ran Fang Wengao Lu Guannan Wang Yacong Zhang Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univer Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univer Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking Univers

A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current at 5V single power supply, with >130 dB DC PSRR performance, occupies an area of 350μm100um, and is of selfbiased characteristic with 2~6 V work supply voltage range.

关键词： Topology Power supplies Poles and zeros Simulation Photonic band gap Frequency estimation Network topology

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An efficient approach to improve PSRR performance of kuijk BGR topology

An efficient approach to improve PSRR performance of kuijk B...

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology

作者： Nie, Hui Lu, Wengao Fang, Ran Wang, Guannan Zhang, Yacong Chen, Zhongjian Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking University Beijing 100871 China School of Software and Microelectronics Peking University Beijing 102600 China

ISBN: (纸本)9781424457984

A highly efficient approach to improve PSRR behavior of Kuijk BGR topology is derived though small signal transfer function analysis and, a BGR circuit has been designed and fabricated on standard 0.5μm CMOS technology to verify this method. This thought greatly relieves the trade-offs of BGR circuit design among power consumption, PSRR performance, area and etc.. This BGR circuit consumes 3μA current at 5V single power supply, with >130 dB DC PSRR performance, occupies an area of 350μmx100μm, and is of self-biased characteristic with 2∼6 V work supply voltage range. ©2010 IEEE.

关键词： Topology

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A Switched-Capacitor Single-ended to Differential Stage for A/D Conversion of IRFPA ROIC

A Switched-Capacitor Single-ended to Differential Stage for ...

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2012 IEEE 11th International Conference on Solid-State and Integrated circuit Technology(ICSICT-2012)

作者： Meng Chen Wengao Lu Guannan Wang Ran Fang Yacong Zhang Zhongjian Chen Lijiu Ji Key laboratory of Microelectronic Devices and Circuit Department of MicroelectronicsPeking University

ISBN: (纸本)9781467324748

This paper presents a Switched-Capacitor Single-ended to Differential（SC-STD）stage for A/D conversion of an Infrared Focal Plane Array（IRFPA）Readout Integration circuit（ROIC）.The SC-STD stage converts the output of the Capacitive Trans-Impedance Amplifier（CTIA）into differential signals,which can be used as the input of the subsequent A/D conversion.A novel Switched-Capacitor Common-Mode Feedback（SC-CMFB）technique with only two capacitors and single phase clock is proposed. Performances of the SC-STD stage are verified by a 14-bit column-paralleled Successive-Approximation A/D converter which is fabricated in a 0.35um CMOS-based process *** SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 *** THD of the SC-STD circuit is up to -94dB at a 1V Vpp input of 1.009 KHz.

关键词： proposed fabricated sampling

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An Offset-compensated Switched-Capacitor Interface circuit for Closed-loop MEMS Capacitive Accelerometer

An Offset-compensated Switched-Capacitor Interface Circuit f...

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2012 IEEE 11th International Conference on Solid-State and Integrated circuit Technology(ICSICT-2012)

作者： Ting-Ting Zhang Hao-Jiong Li Jing-Qing Huang Meng Zhao Li-Chen Hong Ya-Cong Zhang Wen-Gao Lu Zhong-Jian Chen Key Laboratory of Microelectronic Devices and Circuit Department of MicroelectronicsPeking University

This paper presents a switched-capacitor readout circuit designed for the closed-loop MEMS capacitive accelerometer with a full scale of±*** offset voltage of amplifiers is compensated and the low-frequency noise is reduced by using CDS technique, thus the precision of the whole system is significantly *** chip has been fabricated in a 0.35μm 15V CMOS technology and the equivalent noise acceleration (ENA)of the whole accelerometer system is tested to be 950ng/Hz(1/2) at 120Hz in atmosphere.

关键词： Accelerometers Micromechanical devices Equations Sensors Mathematical model Noise Switching circuits

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A Closed-loop System with DC Sensing Method for Vibratory Gyroscopes

A Closed-loop System with DC Sensing Method for Vibratory Gy...

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2012 IEEE 11th International Conference on Solid-State and Integrated circuit Technology(ICSICT-2012)

作者： Tingting Tao Wengao Lu Ran Fang Yacong Zhang Zhongjian Chen Department of Microelectronics Peking University Key laboratory of Microelectronic Devices and Circuit

The paper presents a closed-loop system scheme with DC sensing method for vibratory gyroscopes.A DC sensing method is employed to convert the amplitude-modulated capacitive signal to *** system realizes a closed-loop control in the driving mode.A high voltage(HV)drive signal which is compatible with the gyro is obtained by the on-chip level *** ASIC occupies 2.5×2.0mm 2 in a 0.35μm BCD *** system requires a differential supply of±12V and can work under a resonant frequency from 3 to 10 kHz.

关键词： CSA kHz A Closed-loop System with DC Sensing Method for Vibratory Gyroscopes

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A low-noise interface circuit for MEMS vibratory gyroscope

A low-noise interface circuit for MEMS vibratory gyroscope

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2010 10th IEEE International Conference on Solid-State and Integrated circuit Technology

作者： Fang, Ran Lu, Wengao Liu, Chang Chen, Zhongjian Ju, Yuan Wang, Guannan Ji, Lijiu Yu, Dunshan Key Laboratory of Microelectronic Devices and Circuit Department of Microelectronics Peking University Beijing 100871 China School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA 30332 United States

ISBN: (纸本)9781424457984

A CMOS ASIC has been designed and implemented for readout and control of MEMS vibratory gyroscopes. A low noise design is achieved by using the technique of sinusoidal chopper stabilization with a chopping frequency of 2MHz, which will effectively suppress the low frequency noise. A closed loop control method in driving mode is presented. The Chip is fabricated in a 0.35μm standard CMOS process with an area of 2.5×2.5mm2. The test is performed with a vibratory gyroscope on the condition of closed-loop control, and the measurement result shows a detecting resolution of 6aF in 100Hz bandwidth from a single 5V supply. ©2010 IEEE.

关键词： Timing circuits

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An All-Neuron Spiking 2-D Path Integration and Map Representation Model Implemented on Neuromorphic Chips 16

An All-Neuron Spiking 2-D Path Integration and Map Represent...

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16th IEEE International Conference on Solid-State and Integrated circuit Technology, ICSICT 2022

作者： Liu, Kefei Cui, Xiaoxin Kuang, Yisong Zou, Chenglong Zhong, Yi Xiao, Kanglin Wang, Yuan Peking University Key Laboratory of Microelectronic Devices and Circuits Ministry of Education School of Integrated Circuits Beijing100871 China Peking University Beijing Laboratory of Future Integrated Circuit Technology and Science Beijing100871 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Some specialized neurons have been found in mammalian brains, like grid cells, place cells, head direction cells and speed cells. These neurons form the positioning system in the brain. In this paper, we propose an all-neuron spiking path integration and map representation model dedicated to neuromorphic hardware by mimicking these biological neurons. We deploy a grid cell network on an energy-efficient neuromorphic chip for robot's location representations in 2-D spaces. The grid cell network shifts its activity by integrating motion information from head direction cells and speed cells. With place cells, multiple maps can be stored on one grid cell network. We test our model on several simulated maps and achieve lower path integration error and lower power consumption compared to RatSLAM. We aim to realize an all-neuron robotic control system fully on the neuromorphic chip, and the internal map representation is an important component. © 2022 IEEE.

关键词： Neurons

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