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16th IEEE International Conference on Solid-State and Integrated circuit Technology, ICSICT 2022

作者： Liu, Kefei Cui, Xiaoxin Kuang, Yisong Zou, Chenglong Zhong, Yi Xiao, Kanglin Wang, Yuan Peking University Key Laboratory of Microelectronic Devices and Circuits Ministry of Education School of Integrated Circuits Beijing100871 China Peking University Beijing Laboratory of Future Integrated Circuit Technology and Science Beijing100871 China

ISBN: (数字)9781665469067

ISBN: (纸本)9781665469067

Some specialized neurons have been found in mammalian brains, like grid cells, place cells, head direction cells and speed cells. These neurons form the positioning system in the brain. In this paper, we propose an all-neuron spiking path integration and map representation model dedicated to neuromorphic hardware by mimicking these biological neurons. We deploy a grid cell network on an energy-efficient neuromorphic chip for robot's location representations in 2-D spaces. The grid cell network shifts its activity by integrating motion information from head direction cells and speed cells. With place cells, multiple maps can be stored on one grid cell network. We test our model on several simulated maps and achieve lower path integration error and lower power consumption compared to RatSLAM. We aim to realize an all-neuron robotic control system fully on the neuromorphic chip, and the internal map representation is an important component. © 2022 IEEE.

关键词： Neurons

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Wei, Yanzhao Yao, Jiaxin Xu, Renren Zhang, Qingzhu Yin, Huaxiang Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Institute of Microelectronics Beijing100029 China Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

ISBN: (纸本)9798350311006

In this paper, a La2O3/HfO2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (VFB) negatively shifts 60 mV with sub-1nm La2O3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La2O3/HfO2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology. © 2023 IEEE.

关键词： Timing circuits

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Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation

Unsupervised Learning of Spike-Timing-Dependent Plasticity B...

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IEEE International Conference on Artificial Intelligence circuits and Systems (AICAS)

作者： Yi Zhong Zilin Wang Xiaoxin Cui Jian Cao Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center School of Integrated Circuits Peking University Beijing Laboratory of Future Integrated Circuit Technology and Science Peking University Beijing China

Spiking neural network is a promising endeavor to fulfill brain-like intelligence on the chip. Its learning rule, i.e., spike-timing-dependent plasticity (STDP), derived from neurobiology, is perceived as a powerful candidate to facilitate low-cost and high-performance unsupervised training. In this paper, we present a temporal coding based STDP learning method (TC-STDP) to verify the counter and look-up table based circuit design on a neuromorphic prototype chip. In order to perform on-chip STDP learning in an unsupervised manner, this paper concentrates more on detailing the experimental procedures and practical evaluations, where we introduce the matching score as a quantitative index to carry out label assignment and accuracy confirmation. Evaluation experiments demonstrate that the unsupervised STDP learning achieves best on-chip recognition accuracies of 93.51%, 80.33% on MNIST and EMNIST datasets, respectively. Moreover, experiments conducted on ModelNet40 3D dataset also validate the effectiveness of unsupervised STDP rule to perform possible incremental learning.

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High-Performance PANI Sensor on Silicon Nanowire Arrays for Sub-ppb NH3 Detection

SSRN

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SSRN 2024年

作者： Wang, Zhehang Lan, Kuibo Wang, Zhi Wei, Junqing Chen, Ruibing Qin, Guoxuan Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology School of Microelectronics Tianjin University Tianjin300072 China School of Pharmaceutical Science and Technology Tianjin University Tianjin300072 China Tianjin Key Laboratory of Film Electronic & Communication Devices School of Integrated Circuit Science and Engineering Tianjin University of Technology Tianjin300384 China

For industrial production and disease diagnosis, real-time detection of low concentrations of NH3 is crucial, necessitating a gas-sensitive sensor compatible with integrated processes and exhibiting excellent performance. Herein, we employed wet etching and rapid in situ polymerization on silicon nanowire substrates to grow polyaniline fibers, thereby fabricating NH3 gas sensors with p-p heterojunction and three-dimensional network structures. Characterization and gas sensing performance testing were conducted. The results demonstrate the outstanding NH3 detection capabilities of the sensor, providing stable responses down to concentrations as low as 1 ppb, which indicates its LOD is one to two orders of magnitude lower than current similar products. It also exhibited verified selectivity and long-term reliability. The excellent sensing performance is attributed to the high surface area from the silicon nanowire structure and efficient synergy of p-p heterojunction. Additionally, the influence of doping types of the substrates and annealing process were explored. This work serves as a reference for the design of silicon-based gas sensors with high sensitivity, low detection limits, and extended operational lifetimes, suitable for deployment in commercial integrated monitoring systems. © 2024, The Authors. All rights reserved.

关键词： Heterojunctions

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2 Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yanzhao Wei Jiaxin Yao Renren Xu Qingzhu Zhang Huaxiang Yin Integrated Circuit Advanced Process R&D Center Institute of Microelectronics Chinese Academy of Sciences Beijing China School of Integrated Circuits University of Chinese Academy of Sciences Beijing China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China

In this paper, a La 2 O 3 /HfO 2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (V FB ) negatively shifts 60 mV with sub-1nm La 2 O 3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La 2 O 3 /HfO 2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology.

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Plasmon hybridization induced by quasi bound state in the continuum of graphene metasurfaces oriented for high-accuracy polarization-insensitive two-dimensional sensors

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Chinese Optics Letters 2022年第4期20卷 65-70页

作者： Xiuyu Wang Jihong Xin Qun Ren Haocheng Cai Jiaqi Han Chengyi Tian Pengcheng Zhang Lijie Jiang Zhihao Lan Jianwei You Wei E.I.Sha Tianjin Key Laboratory of Imaging and Sensing Microelectronic Technology School of MicroelectronicsTianjin UniversityTianjin 300072China School of Electrical and Information Engineering Tianjin UniversityTianjin 300072China State Key Laboratory of Millimeter Waves School of Information Science and EngineeringSoutheast UniversityNanjing 210096China Key Laboratory of High Speed Circuit Design and EMC of Ministry of Education School of Electronic EngineeringXidian UniversityXi'an 710071China Huawei Technologies Company Ltd. Shanghai 518129China Department of Electronic and Electrical Engineering University College LondonLondon WC1E7JEUK Key Laboratory of Micro-Nano Electronic Devices and Smart Systems of Zhejiang Province College of Information Science and Electronic EngineeringZhejiang UniversityHangzhou 310027China

Plasmonics could provide compact and powerful solutions for manipulating light in deep-subwavelength dimensions,which is promising for a great range of nanophotonic technologies such as plasmonic rulers and ***,the effective area of enhanced localized field induced by surface plasmon polaritons is typically restricted to the structural *** this work,we propose a method to generate high quality-factor extended electromagnetic fields via hybridizing the superradiant state and the quasi bound state in the continuum of graphene *** coupling interaction involved operates as a three-level system with multiple sharp resonances immune to the polarization,which holds great promise for developing nanodevices with high sensing capacity in two dimensions.

关键词： plasmon hybridization quasi bound state in the continuum high-Q sensing

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Impact of gate length on the electrical characteristics of junctionless FDSOI strained SiGe channel p-FinFET

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Journal of Materials Science: Materials in Electronics 2025年第15期36卷

作者： Lin, Hongxiao Miao, Yuanhao Ren, Yuhui Zhang, Yongkui Zhang, Qingzhu Xiong, Wenjuan Yu, Jiahan Zhao, Xuewei Liang, Renrong Xu, Jun Ye, Tianchun Radamson, Henry H. Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou510535 China School of Microelectronics University of Chinese Academy of Sciences Beijing100049 China School of Integrated Circuits Tsinghua University Beijing100086 China

In this work, we present the influence of structure design on the performance of novel fully depleted silicon-on-insulator (FDSOI) SiGe p-type FinFETs. The effects of Ge content, strain in the epitaxial SiGe channel and gate length (LG) on the device’s electrical characteristics are systematically studied. Among the studied SiGe compositions, Si0.75Ge0.25 exhibits superior performance over Si0.7Ge0.3, as the latter shows the increased defect density due to strain relaxation, degrading carrier transport and the overall device performance. The strain in the Si0.75Ge0.25 channel is tailored to be 0.65% according to the nano beam diffraction (NBD) results, which enhances carrier mobility and drive current (Ion). As the LG decreases from 500 to 30 nm, the device exhibits a well-balanced trade-off between high drive current and low leakage current, demonstrating the effectiveness of the proposed device structure, while the subthreshold swing (SS) shows a progressive deterioration with decreasing LG, reflecting the growing impact of short-channel effects and interface states. At LG = 30 nm, the drain current (Id), maximum transconductance (Gm, max), and Ion/Ioff ratio can reach up to 0.19mA/μm, 33.2μS/μm, and 6.9 × 105, respectively. These improvements were attributed to the enhanced hole mobility from strain engineering and the superior electrostatic control of the junctionless architecture. Our work provides valuable insights into the optimization of junctionless FDSOI FinFETs, enhancing their potential for low-power, high-performance semiconductor applications in the beyond Moore era. © The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2025.

关键词： FinFET

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A novel strategy for GaN-on-diamond device with a high thermal boundary conductance

arXiv

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arXiv 2021年

作者： Mu, Fengwen Xu, Bin Wang, Xinhua Gao, Runhua Huang, Sen Wei, Ke Takeuchi, Kai Chen, Xiaojuan Yin, Haibo Wang, Dahai Yu, Jiahan Suga, Tadatomo Shiomi, Junichiro Liu, Xinyu High-Frequency High-Voltage Device and Integrated Circuits RandD Center Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Department of Mechanical Engineering The University of Tokyo Tokyo Bunkyo113-8656 Japan University of Chinese Academy of Sciences Beijing100049 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Collaborative Research Center Meisei University Tokyo Hino-shi191-8506 Japan Integrated Circuit Advanced Process RandD Center Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China

To achieve high device performance and high reliability for the gallium nitride (GaN)-based high electron mobility transistors (HEMTs), efficient heat dissipation is important but remains challenging. Enormous efforts have been made to transfer a GaN device layer onto a diamond substrate with a high thermal conductivity by bonding. In this work, two GaN-diamond bonded composites are prepared via modified surface activated bonding (SAB) at room temperature with silicon interlayers of different thicknesses (15 nm and 22 nm). Before and after post annealing process at 800 oC, thermal boundary conductance (TBC) across the bonded interface including the interlayer and the stress of GaN layer are investigated by time-domain thermoreflectance and Raman spectroscopy, respectively. After bonding, the 15 nm Si interlayer achieved a higher TBC. The post-annealing significantly increased the TBC of both interfaces, while the TBC of 22 nm silicon interlayer increased greater and became higher than that of 15 nm. Detailed investigation of the microstructure and composition of the interfaces were carried out to understand the difference in interfacial thermal conduction. The obtained stress was no more than 230 MPa for both before and after the annealing, and this high thermal stability of the bonded composites indicates that the room temperature bonding can realize a GaN-on-diamond template suitable for further epitaxial growth or device process. This work brings a novel strategy of SAB followed by high-temperature annealing to fabricate a GaN-on-diamond device with a high TBC. © 2021, CC BY.

关键词： Gallium nitride

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Current Degradation and Delay Analysis of Series-Connected circuits Based on Novel TFET Design

Current Degradation and Delay Analysis of Series-Connected C...

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International Conference on Solid-State and Integrated circuit Technology

作者： Yuan Zhong Cheng Chen Qianqian Huang Zhixuan Wang Le Ye Jenchung Lou Ru Huang Institute of Integrated Circuit Engineering Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

In this paper, for the first time, we investigate the circuit current degradation behavior in series-connected structures based on conventional Tunnel FET (TFET) and our proposed Multi-Finger Schottky-barrier TFET (MFSB-TFET). Due to the suppressed super-linear onset behavior in the output characteristics of MFSB-TFET, the current degradation issue in serious-connected structure for conventional TFET can be much alleviated. Correspondingly, the circuit delay ratio defined as the pull down delay of N-input NAND over the pull down delay of inverter is investigated to character the impact of this issue on circuits. The simulation results reveals that MFSB-TFET has a similar behavior to MOSFET in the series-connected structures while conventional TFET shows much more delay sacrifice.

关键词： Delays TFETs Degradation MOSFET Inverters Topology

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Effect of Mo capping layers thickness on the perpendicular magnetic anisotropy in MgO/CoFeB based top magnetic tunnel junction structure

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Chinese Physics B 2016年第11期25卷 558-562页

作者：刘毅朱开贵钟汇才朱正勇于涛马苏德 School of Physics and Nuclear Energy Engineering Beihang University Key Laboratory of Micro-nano Measurement-Manipulation and Physics Ministry of Education Beihang University Integrated Circuit Advanced Process Center Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences

A detailed study of the magnetic characterizations of the top structure MgO/CoFeB/Mo is *** samples show strong perpendicular magnetic anisotropy（PMA） when the thickness of CoFeB is 0.9 nm and 1.1 *** saturation magnetic moment and interface anisotropy constant are 1566 emu/cm3 and 3.75 erg/cm2,*** magnetic dead layer（MDL） is about 0.23 nm in this ***,strong capping layer thickness dependence is also *** strong PMA of 1.1 nm CoFeB only exists in a Mo cap layer thickness window of 1.2-2 *** maintain PMA,the metal layer could not be too thin or thick in these *** oxidation and diffusion of the metal capping layer should be respectively responsibility for the degradation of PMA in these thin or thick metal capping layer samples.

关键词： anisotropy perpendicular junction annealing annealed thick saturation multilayer responsibility boron

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