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Physical investigation of subthreshold swing degradation behavior in negative capacitance FET

Science China(Information Sciences) 2022年第6期65卷 241-246页

作者： Mengxuan YANG Qianqian HUANG Kaifeng WANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Power consumption has become one of the bottlenecks limiting the future development of integrated circuits. Tunnel FETs(TFETs) and negative capacitance FETs(NCFETs) can break the subthreshold swing limitation(60 mV/dec at room temperature) of conventional metal-oxide-semiconductor field-effect transistor(MOSFET) to reduce the operating voltage and thus power consumption. However, induced by the band-to-band tunneling mechanism, TFETs have a subthreshold swing degradation issue and relatively low ON current. Although NCFETs with ferroelectric/dielectric gate stack can theoretically maintain a high ON current comparable to conventional MOSFET, the physical origin of sub-60 SS is controversial and the mechanism of switching behavior in NCFET is still not clear. In this work, by experimentally investigating the whole negative differential capacitance process and its gate voltage amplification coefficient, an intrinsic issue of SS degradation with increased gate voltage is also found in NCFET for the first time. Based on the physical investigation and simulation results, it is shown that the intrinsic SS degradation in NCFET is resulting from the instant dielectric polarization response. Both the decrease of dielectric thickness and the increase of dielectric constant may lead to the severer SS degradation, which is not favorable for scaled NCFETs.

关键词： ferroelectric negative differential capacitance effect polarization low power voltage amplification

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Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors

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Science China(Information Sciences) 2022年第6期65卷 277-278页

作者： Mengxuan YANG Qianqian HUANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Dear editor,Recently, ferroelectric(FE)-based negative capacitance FET(NCFET) with ferroelectric/dielectric(FE/DE) gate stack has attracted extensive attention due to its capability of sub-60 mV/dec subthreshold swing... 详细信息

关键词： Ferroelectric Negative differential capacitance effect Polarization Low power Subthreshold swing

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A single-inductor thermoelectric, photovoltaic and vibration triplesource energy-harvesting power management system

A single-inductor thermoelectric, photovoltaic and vibration...

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2022 International Conference on Signal Processing and Communication Technology, SPCT 2022

作者： Liang, Zhanrong Wei, Baolin Xu, Weilin Wei, Xuming Gui, Fadi Li, Haiou Key Laboratory of Microelectronic Devices and Integrated Circuits Guilin University of Electronic Technology Guangxi Guilin541004 China

ISBN: (纸本)9781510664333

A single-inductor triple-source energy harvesting system that can harvest thermoelectric, photovoltaic and vibration energy was presented. With an integrated self-starting circuit, the system can self-supply while don't require an external battery. The hybrid modulation of pulse-frequency modulation (PFM) and pulse-width modulation (PWM) is performed to realize adaptive asynchronous control for input and output, achieving higher system stability and better energy aggregation. An adaptive maximum power point tracking (MPPT) was employed to generate inductor charging control signals with different frequencies and duty cycles according to different input sources, enabling the inductor to operate in discontinuous mode (DCM) under different input conditions. The energy harvesting system was designed in a 0.18-μm CMOS process. The simulation results show that the system can realize low-voltage self-startup as low as 200 mV and can provide a stable output of 1.4 V for the load and a 1 V harvested voltage for self-supply. The conversion efficiency of the system is 76.43%@Rload = 10 kΩ, and the average power consumption in sleep mode is 2.38 μW. © 2023 SPIE.

关键词： Energy harvesting

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Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET

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Science China(Information Sciences) 2021年第2期64卷 271-272页

作者： Zhexuan REN Xia AN Gensong LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Strain technology has become a common solution in the semiconductor manufacturing industry since 90-nm technology node to overcome the severe carrier mobility degradation of nanoscale microelectronic devices [1]. Since layout may affect the stress distribution, layout dependent effect(LDE)becomes a serious issue in advanced technology nodes.

关键词： Information Systems and Communication Service

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A Depletion-enhanced N Layers Stacked LDMOS 3

A Depletion-enhanced N Layers Stacked LDMOS

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3rd International Symposium on Semiconductor and Electronic Technology, ISSET 2024

作者： Li, Qi Liang, Lanyi Guan, Li Dang, Tianbao Huang, Hong Chen, Yonghe Guilin University of Electronic Technology Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin541004 China Key Laboratory of Microelectronic Devices and Integrated Circuits Navigation Department of Guangxi Zhuang Autonomous Region Guilin541004 China

ISBN: (纸本)9798350390285

With the development of power integrated circuits, LDMOS devices assume a significant role in power device applications due to their elevated input impedance and enhanced conversion rate. Nonetheless, a contradictory relationship exists between the breakdown voltage and specific on-resistance in power LDMOS devices. Consequently, an n-layer stacked lateral double-diffused metal-oxide-semi conductor transistor(SLDMOS) is proposed, in which numerous MOS cells are stacked under the same chip area. The on-state resistance (R_on) of the n layers S-LDMOS is decreased significantly because of the vertical parallel connection, also the interference among devices is weakened through electrode interconnection isolated by oxidation layer. Multiple drift regions are formed by alternate epitaxy N-layer (drift region) and P-layer (substrate), and each drift region is depleted by the top and bottom P substrates, leading to a much lower R_on. The lightly-doped substrate and N/P top region are used to improve the breakdown characteristics, and the floating P layers are introduced to enhance the depletion effect in drift regions and decrease device thicknesses. By optimizing the configuration, a balanced trade-off is obtained. The simulation results indicate that compared with the traditional LDMOS, the 2 layers S-LDMOS exhibits a BV of 356 V and a specific on resistance (R_on,sp) of 13.56 mΩċ cm2, an improvement of 26.2 % and 71.6%, respectively. And the R_on, sp of n layers S-LDMOS will be reduced to less than 1/n of C-LDMOS further. © 2024 IEEE.

关键词： Power integrated circuits

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Back Gate Controlled Pseudo-P-Channel GaN HFET 3

Back Gate Controlled Pseudo-P-Channel GaN HFET

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3rd International Symposium on Semiconductor and Electronic Technology, ISSET 2024

作者： Guan, Li Li, Qi Liang, Lanyi Wang, Lei Zhang, Xin Li, Haiou Guilin University of Electronic Technology Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin541004 China Key Laboratory of Microelectronic Devices and Integrated Circuits Education Department of Guangxi Zhuang Autonomous Region Guilin541004 China

ISBN: (纸本)9798350390285

This paper proposes a novel pseudo-p-channel AlGaN/GaN heterostructure field-effect transistor (PP-HFET). As semiconductor technology advances, GaN devices are preferred for high-power and high-frequency applications due to their high electron mobility, breakdown field, and wide bandgap. Traditional AlGaN/GaN HFETs perform well because of their high electron density and mobility in the 2DEG channel. However, conventional n-type AlGaN/GaN HFETs are limited in applications requiring p-channel devices. The PP-HFET consists of a top reference electrode and a back-gate control electrode. During operation, the top reference electrode of the PP-HET is biased negatively, rendering the device to be initially in the off state. When a negative voltage is applied to the back gate, the two-dimensional electron gas (2DEG) in the channel is regenerated owing to the compensation effect of the electric field. The more negative the back-gate voltage, the higher the ON current of the device, exhibiting the same characteristics as those of a p-channel device. The effects of the device parameters on the output and transfer characteristics are comprehensively examined, and an analytical model is presented. The simulation results illustrate that the threshold voltage of the proposed device based on the back-gate control is approximately -3.5 V, and the current density is as high as 0.1 A/mm, which is much higher than that of the conventional E-mode p-channel GaN HFET based on two-dimensional hole gas. © 2024 IEEE.

关键词： Gallium nitride

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A 20-Gb/s Low Power Inductorless TIA Design in 0.18μm CMOS 6

A 20-Gb/s Low Power Inductorless TIA Design in 0.18μm CMOS

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6th International Conference on Electronic Engineering and Informatics, EEI 2024

作者： Zeng, Zhiwei Xu, Weilin Mo, Peisi Li, Haiou Key Laboratory of Microelectronic Devices and Integrated Circuits Guilin University of Electronic Technology Education Department of Guangxi Zhuang Autonomous Region Guilin China Guilin University of Electronic Technology Guangxi Key Laboratory of Precision Navigation Technology and Applications Guilin China

ISBN: (纸本)9798350353594

The performance demands on transimpedance amplifiers (TIA) for optoelectronic conversion have increased with the rapid development of fiber optic communication technology. A modified feedforward common gate (MFCG) transimpedance amplifier with an inductor less topology is suggested for analogue front-end wireless fiber optic communications applications. This leads to a significant improvement in the circuit power consumption and band-width. An improved auxiliary amplifier without Miller effect is used instead of the traditional FCG common source amplifier to improve the bandwidth and reduce the phase jitter. An improved parallel active inductor is used instead of the traditional active inductor to obtain a more favorable bandwidth compensation effect. Small-signal analysis demonstrated that the M-FCG has a low input impedance, a large output impedance and transconductance con-version ratio. Based on a 0.18-μm CMOS process post-simulation results, the M-FCG circuit exhibits a transimpedance gain of 58.87 dBΩ, a bandwidth of 6.33 GHz, an equivalent input current noise of 27.02 pA/-VHz, a power consumption of 1.9 mW in the core circuit, and occupies a layout area of 0.0054 mm2. Additionally, the eye diagrams were generated using PRBS at a rate of 20 Gb/s. The resulting eye diagram displays openness and clarity, thereby meeting the requirement for 20 Gb/s code element transmission. © 2024 IEEE.

关键词： CMOS integrated circuits

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Low Power EEPROM Designed for Sensor Interface Circuit

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Chinese Journal of Electronics 2023年第4期21卷 642-644页

作者： Xiangyun MENG Sen YANG Zhongjian CHEN Wengao LU Yacong ZHANG Jingqing HUANG Haojiong LI Weiguo SU Song LI Department of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

EEPROM is an important part for interface circuit of sensor. It saves the calibration data and parameter setting data by non-volatile storage. A new low- power Erasable and electrically programmable read only memory (EEPROM) circuit for sensor interface circuit is introduced in this paper. The data stored in EEPROM can be reloaded automatically by the power-on-reset technique when the power is on. The module consumes power only during power-on-reset and data changing by status optimization and low-power design. This EEPROM circuit has been used in a MEMS accelerometer readout circuit verified by 0.35.μm CMOS EEPROM process. The results are satisfying in that the module can write and store 25bit data and automatically reloads data within 0.1.μs after power-on and then turns to low power mode.

关键词： Micromechanical devices Accelerometers Nonvolatile memory EPROM Calibration Research and development Optimization

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A centripetal collection image sensor(CCIS) based on back gate modulation achieving 1T submicron pixel

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Science China(Information Sciences) 2022年第4期65卷 282-284页

作者： Liqiao LIU Guihai YU Gang DU Xiaoyan LIU Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Image sensors have been rapidly developed for decades and widely used in many different fields [1, 2]. To achieve high resolution, the pixel size has been scaled down to 1 μm for mass production [3]. Nevertheless, the pixel size has to be further reduced to meet the growing demand for higher resolution. In CMOS image sensor(CIS), the pixel is composed of a photodiode, reset transistor,

关键词： Image sensor submicron pixel back gate modulation pixel crosstalk Silicon on insulator

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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2024 IEEE International Electron devices Meeting, IEDM 2024

作者： Li, Chao Yu, Jie Zhang, Xumeng Zhang, Zhaohao Zhu, Fangduo Ouyang, Siyuan Chen, Pei Cheng, Lingli Xu, Gaobo Zhang, Qingzhu Yin, Huaxiang Liu, Qi Liu, Ming State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai200438 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing100029 China

ISBN: (纸本)9798350365429

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000× and 4× improvements than GPU in power consumption and memory overhead. © 2024 IEEE.

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