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An improved single-loop sigma-delta modulator for GSM applications

Journal of Semiconductors 2011年第9期32卷 125-132页

作者：李宏义王源贾嵩张兴 Key Laboratory of Microelectronic Devices and Circuits

Traditional feedforward structures suffer from performance constraints caused by the complex adder before *** paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement *** modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V *** performance satisfies the requirements of a GSM system.

关键词： sigma-delta modulator low-distortion CDS switched-capacitor circuit delayed input feedforward

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Analytical current model of tunneling field-effect transistor considering the impacts of both gate and drain voltages on tunneling

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Science China(Information Sciences) 2015年第2期58卷 174-181页

作者： WANG Chao WU ChunLei WANG JiaXin HUANG QianQian HUANG Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

In this paper, a closed-form current model for bulk tunneling field-effect transistor(TFET) is put forward. Based on the operation mechanism, the channel surface potential φsf which involves the impact of both the gate and the drain voltages is established for the first time. In addition, a new calculation method for the dynamic tunneling width, which is the critical parameter for the TFET modeling, is derived from the surface potential. The surface-potential-based current model is established which is in a good agreement with TCAD simulation results.

关键词： tunneling field-effect transistor current model surface potential drain voltage tunneling width

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Ge surface passivation by GeO2 fabricated by N2O plasma oxidation

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Science China(Information Sciences) 2015年第4期58卷 143-147页

作者： LIN Meng AN Xia LI Ming YUN QuanXin LI Min LI Zhi Qiang LIU PengQiang ZHANG Xing HUANG Ru Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350°C. The transmission electron microscope observation reveals that the Ge O2/Ge interface is automatically smooth and the thickness of Ge O2is～0.9 nm with 120 s N2 O plasma oxidation. The interface state density of Ge surface after N2 O plasma passivation is about～3×1011 cm-2e V-1. With Ge O2 passivation,the hysteresis of MOS capacitor with Al2O3 as gate dielectric is reduced to～55 m V, compared to 130 m V of the untreated one. The Fermi-level at Ge O2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage, which is promising for high performance NMOSFETs fabrication.

关键词： Ge passivation Ge O 2 N 2 O plasma oxidation

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Novel mixed-voltage I/O buffer with thin-oxide CMOS transistors

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Journal of Semiconductors 2009年第7期30卷 83-85页

作者：俞波王源贾嵩张钢刚 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

This paper presents a novel mixed-voltage I/O buffer without an extra dual-oxide CMOS *** mixed-voltage I/O buffer with a simplified circuit scheme can overcome the problems of leakage current and gateoxide reliability that the conventional CMOS I/O buffer *** design is realized in a 0.13-μm CMOS process and the simulation results show a good performance increased by ～34% with respect to the product of power consumption and speed.

关键词： mixed-voltage I/O buffer multi-power domain thin-oxide CMOS

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Fabricating GeO_2 passivation layer by N_2O plasma oxidation for Ge NMOSFETs application

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Chinese Physics B 2014年第6期23卷 538-541页

作者：林猛安霞黎明云全新李敏李志强刘朋强张兴黄如 Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

In this paper, oxidation of Ge surface by N2O plasma is presented and experimentally demonstrated. Results show that 1.0-nm GeO2 is achieved after 120-s N20 plasma oxidation at 300 ℃. The GeO2/Ge interface is atomically smooth. The interface state density of Ge surface after N20 plasma passivation is about - 3 × 1011 ***-1. With GeO2 passivation, the hysteresis of metal-oxide-semiconductor （MOS） capacitor with A1203 serving as gate dielectric is reduced to - 50 mV, compared with - 130 mV of the untreated one. The Fermi-level at GeO2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage.

关键词： Ge GeO2 passivation N2O plasma oxidation Ge NMOSFETs

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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Science China(Information Sciences) 2019年第10期62卷 164-170页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

In this paper, the HfOx-based resistive random access memory（RRAM） devices with sub-100 nm pyramid-type electrodes were fabricated. With the help of tip-enhanced electric field around the pyramid-type electrodes, it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control, lower forming/set voltage（1.97/0.7V） and faster switching speed（≤30 ns under 0.9V pulse） as well as better endurance reliability than conventional flat electrode resistive memory devices. In addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling down. This novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection

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Science China(Information Sciences) 2019年第6期62卷 79-86页

作者： Lizhong ZHANG Yuan WANG Yize WANG Xing ZHANG YANDong HE Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of MicroelectronicsPeking University

A conventional diode-triggered silicon-controlled rectifier(DTSCR) structure with a layout strategy for electrostatic discharge(ESD) protection is presented and confirmed in a 65-nm CMOS *** modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing(TLP)/very fast transmission line pulsing(VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model(CDM) event.

关键词： diode triggered silicon controlled rectifier(DTSCR) electrostatic discharge(ESD) transmission line pulsing(TLP) very fast transmission line pulsing(VF-TLP) turn-on behavior

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Vertical SnS2/Si heterostructure for tunnel diodes

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Science China(Information Sciences) 2020年第2期63卷 189-195页

作者： Rundong JIA Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University

Tunneling FET（TFET） is considered as one of the most promising low-power electronic devices,however, suffers from the low drive current. Heterostructure TFET with low effective tunnel barrier height based on traditional 3D materials can obtain large tunnel current but deteriorated off-state current induced by the lattice mismatch. van der Waals heterostructure TFET based on 2D materials can obtain danglingbond-free interface for suppressed off-state current but face the challenge of controllable and stable doping technology. As the critical building block of the TFET, tunnel diode based on the 2D/3D heterostructure is proposed in this study and experimentally demonstrated. Combination of the pristine interface of 2D materials and matured doping technology in the traditional 3D bulk materials, tunnel diodes based on the 2D/3D heterostructures are expected to realize low leakage current and high on current simultaneously,showing great potential in low-power electronics. The N+SnS2/P+Si heterostructure with effective tunnel barrier of 0.17 eV theoretically is considered for the first time and selected as the optimal material platform for tunnel diodes. The N+SnS2/P+Si tunnel diode demonstrated experimentally shows the high current density of 1 μA/μm2, which is the highest one among the reported tunnel diodes based on the 2D/group IV materials. The tunneling current is also confirmed by low-temperature measurements. This study shows the great potential of the 2D/3D heterostructure for low-power tunneling devices.

关键词： 2D/3D heterostructure SnS2/Si tunnel barrier tunnel diode energy-efficient

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Low-power CMOS fully-folding ADC with a mixed-averaging distributed T/H circuit

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Journal of Semiconductors 2009年第12期30卷 128-132页

作者：刘振贾嵩王源吉利久张兴 Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

This paper describes an 8-bit 125 MHz low-power CMOS fully-folding analog-to-digital converter （ADC） A novel mixed-averaging distributed T/H circuit is proposed to improve the accuracy. Folding circuits are not only used in the fine converter but also in the coarse one and in the bit synchronization block to reduce the number of comparators for low power. This ADC is implemented in 0.5μm CMOS technology and occupies a die area of 2 × 1.5 mm^2. The measured differential nonlinearity and integral nonlinearity are 0.6 LSB/-0.8 LSB and 0.9 LSB/-1.2 LSB, respectively. The ADC exhibits 44.3 dB of signal-to-noise plus distortion ratio and 53.5 dB of spurious-free dynamic range for 1 MHz input sine-wave. The power dissipation is 138 mW at a sampling rate of 125 MHz at a 5 V supply.

关键词： analog-to-digital converter low power fully-folding mixed-averaging distributed T/H circuit bit synchronization

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A VCO sub-band selection circuit for fast PLL calibration

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Journal of Semiconductors 2009年第8期30卷 153-155页

作者：宋颖王源贾嵩赵宝瑛 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

关键词： PLL VCO calibration

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