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IEEE Conference on Electron devices and Solid-State circuits

作者： Wanlu Wang Song Jia Ziyi Wang Tao Pan Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781538662359

Two low voltage dual-modulus frequency divider based on extended true single-phase clock (E-TSPC) logic are proposed. By reducing the number of serial transistors from VDD to GND, the proposed designs can effectively work at low voltage. Simulation results in SMIC 40nm technology show that the presented design I has better power and speed performance with lower supply voltage. Compared to the referenced designs, the presented design II can work at the lowest supply voltage with little loss of performance.

关键词： Low voltage Transistors Power demand Clocks Frequency conversion Robustness CMOS technology

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Switching Dynamics and Computing Applications of Memristors:An Overview 12

Switching Dynamics and Computing Applications of Memristors:...

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2017 IEEE 12th International Conference on ASIC

作者： Qingxi Duan Teng Zhang Minghui Yin Caidie Cheng Liying Xu Yuchao Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University

ISBN: (纸本)9781509066261;9781509066254

Memristors have acquired a lot of attention due to their potential applications in nonvolatile memory,reconfigurable logic,analog circuits and neuromorphic computing etc.,and important progress has been made *** we first shed light on the switching dynamics of oxide based memristors by electrostatic force microscopy(EFM).We further demonstrate a new type of vertical 3-terminal oxide based memristive device capable of implementing heterosynaptic *** address the long-standing issue of device variations in memristors limiting the construction of neuromorphic computing systems,we propose a fuzzy restricted Boltzmann machine(FRBM) network that can effectively tolerate device ***,we show that nonvolatile Boolean logic can also be achieved in the same 3-terminal heterosynaptic devices in an efficient manner,compared with conventional 2-terminal memristors.

关键词： memristors switching dynamics neuromorphic computing nonvolatile logic fuzzy restricted Boltzmann machine(FRBM) network

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A Physical Current Model for Self-Depleted T-gate Schottky Barrier Tunneling FET with Low SS and High ION/IOFF

A Physical Current Model for Self-Depleted T-gate Schottky B...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jin Luo Zhu Lv Qian-Qian Huang Cheng Chen Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

Compared with conventional tunneling field-effect transistor (TFET), the novel T-gate Schottky barrier TFET (TSB-TFET) with adaptive operation mechanism can effectively achieve higher I ON with dominant Schottky current, lower I OFF by introducing self-depleted effect and steep subthreshold slope with dominant band-to-band tunneling current. To facilitate the circuit simulation based on this new kind of device, in this paper, we establish a physical current model of TSB-TFET through modeling its modulated band-to-band tunneling and Schottky barrier injection current respectively. The current model results with different device parameters agree well with Sentaurus TCAD simulation results, showing its high applicability for further circuit design and simulation.

关键词： Junctions Schottky barriers Tunneling TFETs Logic gates Integrated circuit modeling Fingers

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Current Mirrors Based on Graphene Field-effect Transistors

Current Mirrors Based on Graphene Field-effect Transistors

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International Conference on Solid-State and Integrated Circuit Technology

作者： Pei Peng Zhongzhen Tian Muchan Li Zidong Wang Liming Reng Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

Current mirrors are significant elements in analog integrated circuits. Here, graphene-based field-effect transistors (GFETs) are fabricated and the parameters of device model for the fabricated GFETs are extracted from the measured I-V characteristics. The GFETs model was then coded with Verilog-A language for circuit simulation. Using simulation, we investigate the electrical properties of GFETs-based current mirrors. We found that in simple current mirror configuration, the output current is intensively dependent on the output voltage, and cannot track the reference current well. However, in GFETs-based cascode current mirror configuration, the output current can track the reference current in a proper range of output voltage, indicating the GFETs can implement cascode current mirrors. Furthermore, the GFETs-based cascode current mirror working as a load can efficiently improve the voltage gain of the GFETs-based amplifiers when compared to a resistor load.

关键词： Mirrors Graphene Integrated circuit modeling Logic gates Resistors Analytical models Current measurement

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Nonvolatile memristor as a new platform for non-von Neumann computing

Nonvolatile memristor as a new platform for non-von Neumann ...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Liying Xu Lin Bao Teng Zhang Ke Yang Yimao Cai Yuchao Yang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

Nonvolatile logic based on memristors provides a promising approach toward efficient Non-von Neumann computing. Here we propose a methodology employing hybrid bipolar-unipolar memristive circuits for efficient in-memory logic functions. By combining the features of bipolar and unipolar memristors, the proposed circuits are able to execute both fundamental Boolean logic and arithmetic computing with high reconfigurability and high parallelism, which compares favorably with existing methods of in-memory logic based on memristors. This work could thus pave the way for the development of new in-memory computing architecture with high efficiency.

关键词： Memristors Adders Logic arrays Logic functions Logic gates Nonvolatile memory Parity check codes

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Insight into multiple-triggering effect in DTSCRs for ESD protection

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Journal of Semiconductors 2017年第7期38卷 93-96页

作者： Lizhong Zhang Yuan Wang Yize Wang Yandong He Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking UniversityBeijing 100871 China

The diode-triggered silicon-controlled rectifier（DTSCR） is widely used for electrostatic discharge（ESD） protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse（TLP） test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multipletriggering effect.

关键词： electrostatic discharge（ESD） diode-triggered silicon-controlled rectifier（DTSCR） double snapback transmission line pulse（TLP） test

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A Low Power High Output Frequency Two-stage Output Buffer for 2720X2704 Infrared Focal Plane Array

A Low Power High Output Frequency Two-stage Output Buffer fo...

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IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Meicen Jin Yuze Niu Wengao Lu Yacong Zhang Zhongjian Chen Yi Zhuo Peking University Information Technology Institute (Tianjin Binhai) China Key Laboratory of Microelectronic Devices and Circuits Peking University China

This paper presents a low power high output frequency readout integrated circuit(ROIC) for 2720 X 2704 cryogenic infrared focal plane array (IRFPA). A two-stage output buffer is proposed to reduce power consumption and improve output frequency. This ROIC has been designed and fabricated in 0.35um CMOS technology and chip size is 44mmx46mm. The ROIC implements a dynamic range of 86dB and a readout rate of 10MHz while consumes only 180mW.

关键词： IRFPA ROIC proposed

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A 781Mbps-5Gbps DLL-Based CDR with Starting-Control Circuit

A 781Mbps-5Gbps DLL-Based CDR with Starting-Control Circuit

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IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Cheng Li Yuequan Liu Song Jia Yuan Wang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing P. R. China

This paper presents a 781 Mbps-5 Gbps wide-range clock and data recovery (CDR) circuit combined delay-locked loop (DLL). A novel starting-control circuit is introduced to solve the inherent problem of false locking and expand the phase capture range. The phase detector (PD) achieves sampling and charge-pump tasks in one pass-gate construction, which optimizes the design complexity and cost. The results demonstrate the peak-to-peak jitter is 5.74 ps and the total power consumption is 4.6 mW at 4 Gbps with 1.2V power supply.

关键词： DLL-Based CDR PD

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Current Degradation and Delay Analysis of Series-Connected circuits Based on Novel TFET Design

Current Degradation and Delay Analysis of Series-Connected C...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Yuan Zhong Cheng Chen Qianqian Huang Zhixuan Wang Le Ye Jenchung Lou Ru Huang Institute of Integrated Circuit Engineering Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

In this paper, for the first time, we investigate the circuit current degradation behavior in series-connected structures based on conventional Tunnel FET (TFET) and our proposed Multi-Finger Schottky-barrier TFET (MFSB-TFET). Due to the suppressed super-linear onset behavior in the output characteristics of MFSB-TFET, the current degradation issue in serious-connected structure for conventional TFET can be much alleviated. Correspondingly, the circuit delay ratio defined as the pull down delay of N-input NAND over the pull down delay of inverter is investigated to character the impact of this issue on circuits. The simulation results reveals that MFSB-TFET has a similar behavior to MOSFET in the series-connected structures while conventional TFET shows much more delay sacrifice.

关键词： Delays TFETs Degradation MOSFET Inverters Topology

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A Self-Adaptive Digital Calibration Technique for MultiChannel High Resolution Capacitive SAR ADCs 12

A Self-Adaptive Digital Calibration Technique for MultiChann...

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2017 IEEE 12th International Conference on ASIC

作者： Binbin Lyu Wengao Lu Sijia Yang Zhongjian Chen Yacong Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University Peking University Information Technology Institute(Tianjin Binhai)

ISBN: (纸本)9781509066261;9781509066254

This paper introduces a self-adaptive digital technique to calibrate multi-channel SAR *** than achieving higher resolution by adjusting the analog component values,this new digital method infers the capacitor weights of a SAR ADC with the help of a channel-shared high resolution sigma-delta ADC,which results in remarkable improvements in the capacitive SAR ADCs' *** increases from 11.06 bits to 12.67 *** digital calibration logic is based on LMS(least mean squares) and gradient descent.

关键词： SAR ADC multi-channel digital calibration

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