In this paper, a new Voltage-to-Time Converter design is presented. The proposed scheme is based on a new current starved inverter with its analog input adopting a folding structure. Better linearity is achieved for t...
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In this paper, a new Voltage-to-Time Converter design is presented. The proposed scheme is based on a new current starved inverter with its analog input adopting a folding structure. Better linearity is achieved for the new scheme. Proposed VTC can accept +/-0.5V at 5GS/s sampling rate with a linearity maximum error of 2.5%. The simulation results show that an ENOB of 7.5 bits is achieved with an output range of +/-51ps in 65nm CMOS process.
This paper presents a digital dimming control circuit used in a light-emitting diode(LED) driver, allowing it to dim multiple LED strings with only two input ports which receive serial data accompanied with synchron...
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ISBN:
(纸本)9781467397209
This paper presents a digital dimming control circuit used in a light-emitting diode(LED) driver, allowing it to dim multiple LED strings with only two input ports which receive serial data accompanied with synchronous clock. A multiplexing technique is used to simplify the control circuit, using one DAC to transfer all the dimming messages for each string, and a real-time refresh technique is used to make the transferred dimming voltage keep a high accuracy all the time. The circuit is friendly compatible with the linear current regulator and pulsewidth modulation(PWM) dimming methods. To get a precise dimming control, we build a 10-bit segment R-2R DAC. The simulation results show the dimming voltages for each LED string keep the errors less than 0.5LSB compared with the designed voltages.
We demonstrate a facile method to grow highly uniform monolayer graphene films on copper foils by atmospheric pressure chemical vapor deposition(APCVD). The technique in this method includes lowering flow ratio of m...
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ISBN:
(纸本)9781467397209
We demonstrate a facile method to grow highly uniform monolayer graphene films on copper foils by atmospheric pressure chemical vapor deposition(APCVD). The technique in this method includes lowering flow ratio of methane/hydrogen and extending exposure time to hydrogen. All the multilayer islands will be etched away by hydrogen during this growth process, resulting in obtaining highly uniform monolayer graphene. A mechanism for the suppression of mutilayer spots based on the etching effect of hydrogen is *** electron and hole room-temperature mobilities for the back-gated graphene transistors are up to about 3800cmVs and 3300 cmVs, respectively.
The photocurrent in graphene has drawn much attention in recent years. The mechanisms of its production vary in different situations, such as at the interfaces of monolayer-bilayer junction or p-n junction. Here we de...
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ISBN:
(纸本)9781467397209
The photocurrent in graphene has drawn much attention in recent years. The mechanisms of its production vary in different situations, such as at the interfaces of monolayer-bilayer junction or p-n junction. Here we demonstrate photocurrent generation in graphene-based field-effect transistors(GFETs) with a partially suspended area. Both Raman and photocurrent mapping were performed after a laser-induced doping under vacuum at room temperature. The resulting photocurrent in the suspended area is an order of magnitude larger than that in the supported area. The difference in photocurrent may be attributed to the thermoelectric effect.
In this paper, a closed-form current model for bulk tunneling field-effect transistor(TFET) is put forward. Based on the operation mechanism, the channel surface potential φsf which involves the impact of both the ga...
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In this paper, a closed-form current model for bulk tunneling field-effect transistor(TFET) is put forward. Based on the operation mechanism, the channel surface potential φsf which involves the impact of both the gate and the drain voltages is established for the first time. In addition, a new calculation method for the dynamic tunneling width, which is the critical parameter for the TFET modeling, is derived from the surface potential. The surface-potential-based current model is established which is in a good agreement with TCAD simulation results.
In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350...
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In this paper, Ge surface passivation by Ge O2 grown by N2 O plasma oxidation is presented and experimentally demonstrated. Results show that stoichiometrically Ge O2 can be achieved by N2 O plasma oxidation at 350°C. The transmission electron microscope observation reveals that the Ge O2/Ge interface is automatically smooth and the thickness of Ge O2is~0.9 nm with 120 s N2 O plasma oxidation. The interface state density of Ge surface after N2 O plasma passivation is about~3×1011 cm-2e V-1. With Ge O2 passivation,the hysteresis of MOS capacitor with Al2O3 as gate dielectric is reduced to~55 m V, compared to 130 m V of the untreated one. The Fermi-level at Ge O2/Ge interface is unpinned, and the surface potential is effectively modulated by the gate voltage, which is promising for high performance NMOSFETs fabrication.
In this paper, the challenge of gate-all-around nanowire transistor for low power application is uncovered and discussed from experimental and TCAD simulation. For promising low power application, gate-all-around nano...
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In this paper, the challenge of gate-all-around nanowire transistor for low power application is uncovered and discussed from experimental and TCAD simulation. For promising low power application, gate-all-around nanowire transistor faces more difficulties than expected due to abnormal gate-induced-drain-leakage current behavior. The study shows that as nanowire diameter shrinks, GIDL current will become worse rather than suppressed. The gate coupling modulated drain-to-body electric field is found responsible for the increased GIDL current in the extremely scaled nanowire. To overcome the challenge of GAA SNWT in low power application, a practical design is proposed by optimization of overlap length and drain junction gradient considering the trade-off between short channel effect and performance.
In this paper, the impact of structure and material of hard mask wet trimming (HMWT) process on the formation of Si Fins and their LER/LWR is investigated experimentally. Combining a capping layer with slow wet etchin...
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In this paper, the impact of structure and material of hard mask wet trimming (HMWT) process on the formation of Si Fins and their LER/LWR is investigated experimentally. Combining a capping layer with slow wet etching rate can effectively improve HMWT controllability and suppress LER/LWR of Si Fins. Based on the optimized HMWT, ultranarrow Si Fins with 5nm width and 40x aspect ratio is successfully fabricated.
In this paper, a novel nitrogen plasma pretreatment (NPP) has been experimentally demonstrated to improve the thermal stability of thin NiGe film. The root mean square (RMS) roughness of NiGe film pretreated by NPP te...
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In this paper, a novel nitrogen plasma pretreatment (NPP) has been experimentally demonstrated to improve the thermal stability of thin NiGe film. The root mean square (RMS) roughness of NiGe film pretreated by NPP technique is reduced to 0.52nm, illustrating more uniform and smooth NiGe film than that without pretreatment. The thermal stability of NiGe film is improved to at least 600°C by this technique. The NPP process time is also optimized to be 30s~120s. The very thin interfacial layer of GeN x formed on Ge surface by NPP technique is believed to suppress oxygen diffusion, thus improving the surface morphology of NiGe film. The formation of Ge-N and/or Ni-N chemical bonds, which inhibits the agglomeration of NiGe, may also help to improve the thermal stability. Therefore, this technique shows great potential for Ge-based technology.
In this work, a feasible multi-V T modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that ha...
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In this work, a feasible multi-V T modulation strategy in vertical nanowire FETs (VNWFETs) combining asymmetric halo doping with nanowire diameter is proposed and verified by TCAD simulation. The results show that halo configuration close to source side exhibits larger V T -tuning range and better SCE controlling. Moreover, adjustment of halo doping concentration and nanowire diameters can be adopted to provide at least three V T choices for 7nm technology node. It is demonstrated that VNWFETs is quite promising for SOC application.
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