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A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC for X-ray sensor array 7

A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC...

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7th IEEE International Nanoelectronics Conference, INEC 2016

作者： Zhang, Zhuo Zhang, Yacong Fair, Miaomiao Zhao, Meng Liu, Dahe Lu, Wengao Chen, Zhongjian Peking University Shenzhen Graduate School Shenzhen518055 China Key Laboratory of Microelectronic Devices and Circuits Institute of Micro and Nano Electronics Peking University Beijing100871 China Beida Information Research Tianjin300452 China

ISBN: (纸本)9781467389693

This paper presents a column-level 14-bit two-stage analog-to-digital converter (ADC) based on pseudo-differential operational amplifier, which is designed for the readout circuit of X-ray sensor array. This low-power hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same analog circuit to reduce area and power consumption. A test chip is fabricated in 0.18μm CMOS technology. The hybrid ADC in each column is performed in parallel with power consumption of 218.813μW. The simulation result reveals the effective number of bits (ENOB) is 13.775 bits. © 2016 IEEE.

关键词： Operational amplifiers

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A New Static Power Clamp Co-designed with Input ESD Protection Circuit

A New Static Power Clamp Co-designed with Input ESD Protecti...

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2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)

作者： Jian Wang Jian Cao Guangyi Lu Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University

A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and the excellent ESD performance.

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Novel insights into the power-off and power-on transient performance of power-rail ESD clamp circuit

Novel insights into the power-off and power-on transient per...

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Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

作者： Guangyi Lu Yuan Wang Yize Wang Jian Cao Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing P.R. China

ISBN: (纸本)9781467389266

Based on the thorough characterization of the transient performance of a power-rail ESD clamp circuit, novel insights concerning the bigFET response time, power-off triggering criteria and power-on noise immunity with respect to the disturbance waveform are clearly summarized in this work. The instructive qualities of these insights are deeply discussed.

关键词： Transient analysis Electrostatic discharges Time factors Clamps Logic gates Integrated circuits

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A novel MASH 2-1 sigma-delta A/D converter with high-to-low conversion for closed-loop MEMS accelerometer interface

A novel MASH 2-1 sigma-delta A/D converter with high-to-low ...

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IEEE International Nanoelectronics Conference (INEC)

作者： Hongzhe Li Feng Wu Meng Zhao Zhongjian Chen Wengao Lu Yacong Zhang Key Laboratory of Microelectronic Devices and Circuits Peking University Shenzhen China Beida (Binhai) Information Research Tianjin China

ISBN: (纸本)9781467389709

In this paper, an A/D converter offering the high-to-low level shifter function applied to the high range digital closed-loop MEMS accelerometer interface is presented. In the interface circuit, the analog front-end circuit works in the high-voltage domain and the digital back-end circuit works in the low-voltage domain, however, the cascade MASH 2-1 sigma-delta ADC just can achieve high-voltage signal converting to low-voltage signal without introducing additional high-to-low transition module. The level shifter is mainly realized by the first integrator by means of using switched-capacitor charge transfer principle. The cascade MASH 2-1 sigma-delta ADC performs a maximum signal-to-noise-plus-distortion ratio (S/(N+D)) rms/rms of 113.6 dB with 200 Hz bandwidth and sampling clock of 100-kHz. The interface was designed in TSMC 0.35 um CMOS process and was sent to the foundry to prototype.

关键词： Accelerometers Multi-stage noise shaping Sigma-delta modulation Micromechanical devices Capacitance Modulation

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A wafer-level characterization method of ESD protection circuits for both component-level and system-level applications

A wafer-level characterization method of ESD protection circ...

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Asia-Pacific Symposium on Electromagnetic Compatibility (APEMC)

作者： Yuan Wang Guangyi Lu Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing P.R. China

Electrostatic discharge (ESD) protection circuits are often designed with detection circuits to trigger clamp devices to bypass ESD currents. In order to fully characterize performance of these protection circuits, a wafer-level characterization method is proposed in this work. By separating the detection rail from the supply rail, triggering actions resulted from detection circuits can be clearly captured by the proposed method. Besides, both the component-level triggering criteria and system-level transient-induced latch-up (TLU) immunity of ESD protection circuits can be fully characterized by the proposed method. Silicon-data based case studies are presented in this work to verify the validity of the proposed method.

关键词： Capacitance Levee

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Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics

Delay-locked loop based frequency quadrupler with wide opera...

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International Symposium on circuits and Systems

作者： Yuan Wang Yuequan Liu Mengyin Jiang Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University 100871 Beijing P.R. China

ISBN: (纸本)9781479953424

A wide operating range and fast locking delay-locked loop (DLL) based frequency quadrupler that includes an eight-phase-clock generator and an edge combiner is proposed. The eight-phase-clock generator is composed of a coarse-code generator, a fine-code generator and a digital controlled delay line, which uses four differential delay units to generate equally spaced eight-phase clocks. The coarse-code generator adopts a time-to-digital scheme to achieve short locking time and wide operating range. A fine-code digital-to-analog converter in the fine-code generator converts the fine codes to analog voltage for high precision. Moreover, the novel edge-combiner circuit combines the eight-phase clocks to ×4 frequency output with 50% duty cycle ratio. Experimental results in a 65-nm CMOS process show this frequency multiplier can cover a frequency range from 320 MHz to 2.4 GHz and cost 5～40 cycles to finish locking.

关键词： fast locking quadrupler delay-locked loop (DLL) eight-phase-clock generator edge-combiner wide operating range

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A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications

A novel low-leakage power-rail ESD clamp circuit with adjust...

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International Symposium on circuits and Systems

作者： Guangyi Lu Yuan Wang Jian Cao Song Jia Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of Microelectronics Peking University Beijing 100871 P.R. China

ISBN: (纸本)9781479953424

This work presents a novel power-rail electrostatic discharge (ESD) clamp circuit for nanoscale applications. By skillfully incorporating transient and static ESD detection mechanisms into its detection circuit, the proposed circuit achieves a wide range of adjustable triggering voltage (Ft1) while maintaining low standby leakage current (Ileak). Besides, the proposed circuit achieves significantly-improved false-triggering immunity compared with the transient-triggered circuit. All investigated circuits are fabricated in a 65-nm CMOS process. Simulation and test results have both confirmed the superiority of the proposed circuit. In addition, the proposed circuit achieves similar triggering behaviors in both transmission line pulsing (TLP) and very fast TLP (VF-TLP) tests.

关键词： transmission line pulsing (TLP) test Electrostatic discharge (ESD) detection circuit triggering voltage (Vt1) leakage current (Ileak)

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Series resistance of signal line in graphene coplanar waveguide

Series resistance of signal line in graphene coplanar wavegu...

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China Semiconductor Technology International Conference (CSTIC)

作者： Zidong Wang Xiongjun Shu Yuehui Jia Pei Peng Xin Gong Liming Ren Jincai Wen Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China Key Laboratory for RF Circuits and Systems (MOE) Hangzhou Dianzi University Hangzhou China School of Physics Peking University Beijing China

In this paper, we focus on the influence of series resistance of signal line (comoprised of the sheet resistance of graphene and the contact resistance between graphene and metal) on the radio-frequency transmission property of graphene coplanar waveguide (CPW) and put forward ways to improve it. According to our research, the large series resistance (7.2 kΩ) of signal line is the main reason for the large insertion loss (|S 21 |) of graphene CPW. The insertion loss of graphene CPW is found to be reduced by either enlarging the area of graphene-metal contact or increasing the number of graphene layers.

关键词： Graphene Coplanar waveguides Resistance Metals Radio frequency Insertion loss Equivalent circuits

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A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC for X-ray sensor array

A low-power 14-bit hybrid incremental sigma-delta/cyclic ADC...

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IEEE International Nanoelectronics Conference (INEC)

作者： Zhuo Zhang Yacong Zhang Miaomiao Fair Meng Zhao Dahe Liu Wengao Lu Zhongjian Chen Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China Beida (Binhai) Information Research Tianjin China Peking University Beijing Beijing CN

ISBN: (纸本)9781467389709

关键词： Power demand Sensor arrays Hybrid power systems Analog circuits X-ray imaging Clocks Analog-digital conversion

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A Low-power 14-bit Two-stage Hybrid ADC for Infrared Focal Plane Array Detector

A Low-power 14-bit Two-stage Hybrid ADC for Infrared Focal P...

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2016 IEEE Information Technology,Networking,Electronic and Automation Control Conference(ITNEC 2016)

作者： Zhuo Zhang Yacong Zhang Miaomiao Fan Meng Zhao Dahe Liu Wengao Lu Zhongjian Chen Peking University Shenzhen Graduate School Key Laboratory of Microelectronic Devices and Circuits Institute of Micro & Nano ElectronicsPeking University Beida (Binhai) Information Research

ISBN: (纸本)9781467391955

this paper presents a low-power 14-bit hybrid incremental Σ-Δ/cyclic analog-to-digital converter(ADC) based on pseudo-differential operational amplifier, which is designed for the readout circuit of infrared focal plane array *** two-stage hybrid ADC employs an incremental sigma-delta ADC and a cyclic ADC, achieving a good trade-off between accuracy and conversion speed. The two stages share the same analog circuit to reduce area and power consumption. A common-mood feedback module is used to suppress the influence of charge injection, and the effectiveness is demonstrated by detailed theoretical analysis and simulation result. A test chip is fabricated in 0.18 μm CMOS technology. The hybrid ADC in each column is performed in parallel with power consumption of218.813 μW. The simulation result reveals the effective number of bits(ENOB) is 13.775 bits.

关键词： hybrid ADC incremental sigma-delta cyclic low power infrared array detector

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