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Heavy ion induced electrical property degradation in sub-100 nm bulk silicon MOS devices

Journal of Semiconductors 2015年第11期36卷 30-33页

作者：陈叶华安霞武唯康张曜刘静静张兴黄如 Peking University Shenzhen Graduate School Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University School of Software and Microelectronics Peking University

The radiation response of 90 nm bulk silicon MOS devices after heavy ion irradiation is experimentally investigated. Due to the random strike of the incident particle, different degradation behaviors of bulk silicon MOS devices are observed. The drain current and maximum transconductance degrade as a result of the displacement damage in the channel induced by heavy ion strike. The off-state leakage current degradation and threshold voltage shift are also observed after heavy ion irradiation. The results suggest that the radiation induced damage of sub-100 nm MOS devices caused by heavy ion irradiation should be paid attention.

关键词： heavy ion displacement damage bulk silicon

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New approach for understanding “random device physics” from channel percolation perspectives: Statistical simulations, key factors and experimental results

New approach for understanding “random device physics” fro...

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International Electron devices Meeting (IEDM)

作者： Zhe Zhang Zexuan Zhang Runsheng Wang Xiaobo Jiang Shaofeng Guo Yangyuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China Innovation Center for MicroNanoelectronics and Integrated System Beijing China Synopsys Glasgow U.K

ISBN: (纸本)9781509039036

The concept of percolative channel is essential for understanding statistical variability and reliability in nanoscale transistors. In this paper, the quantitative factors of channel current percolation path (PP) are comprehensively studied in planar and FinFET devices for the first time, with statistical simulations and experimental characterizations. The properly-defined PP parameters are well quantified by the proposed new approach, and extracted from `atomistic' device simulation. The experimental data of random telegraph noise (RTN) is used via the atomic PP model to characterize the underlying channel local current fluctuations and thus to benchmark the PP in reality. Experimental results of extracted PP parameters are consistent with those predicted from simulations, confirming the effectiveness of the proposed approach. The 3D PP in FinFET has different features compared with 2D PP in planar devices, and exhibits additional distortion along Fin-width direction. This work provides a unique framework for deep understanding of “random device physics” and thus is helpful for future nano-device design.

关键词： FinFETs Current density Fluctuations Distortion Physics Three-dimensional displays

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A new static power clamp co-designed with input ESD protection circuit

A new static power clamp co-designed with input ESD protecti...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Jian Wang Jian Cao Guangyi Lu Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Peking University Beijing Beijing CN Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781467397209

A new static power clamp circuit integrated with input ESD protection is proposed in this paper. By skillfully incorporating traditional input ESD protection, the proposed circuit replaces the protection resistor by the active switch and merging the signal control circuit into trigger circuit of static power clamp. The proposed circuit is a whole-chip ESD protection scheme that has a low leakage and the excellent ESD performance.

关键词： Electrostatic discharges Clamps Logic gates Switching circuits Stress MOS devices Leakage currents

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Deep Insights into Dielectric Breakdown in Tunnel FETs with Awareness of Reliability and Performance Co-Optimization

Deep Insights into Dielectric Breakdown in Tunnel FETs with ...

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IEEE International Electron devices Meeting

作者： Qianqian Huang Rundong Jia Jiadi Zhu Zhu Lv Jiaxin Wang Cheng Chen Yang Zhao Runsheng Wang Weihai Bu Wenbo Wang Jin Kang Kelu Hua Hanming Wu Shaofeng Yu Yangyuan Wang Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Semiconductor Manufacturing International Corporation (SMIC) Shanghai 201203 and Beijing 100176 China

ISBN: (纸本)9781509039036

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

关键词： Tunnel FETs Awareness Reliability

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Observation of sub-20nm line-defects in graphene by friction force microscopy

Observation of sub-20nm line-defects in graphene by friction...

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China Semiconductor Technology International Conference (CSTIC)

作者： Yuehui Jia Zidong Wang Xin Gong Pei Peng Liming Ren Yunyi Fu Han Zhang Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China School of Electronic and Computer Engineering Peking University Shenzhen Graduate School Shenzhen China State Key Laboratory for Mesoscopic Physics Peking University Beijing China

Graphene films, produced by chemical vapor deposition (CVD) on copper foils, generally have a lot of line-defects, such as grain boundaries and nanogaps between adjacent graphene domains. We demonstrated to identify such 1-D defects with size less than 20 nanometers using friction force microscopy (FFM). These line defects can be clearly observed in friction force images, while no height variation in simultaneously collected topographic ones. The possible reasons for line defects imaging under FFM mode is also studied.

关键词： Graphene Friction Surface topography Copper Force Microscopy Films

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Contact resistance between graphene and metal

Contact resistance between graphene and metal

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China Semiconductor Technology International Conference (CSTIC)

作者： Ce Yang Zidong Wang Yuehui Jia Pei Peng Xin Gong Liming Ren Yunyi Fu Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China School of Physics Peking University Beijing China School of Electronic and Computer Engineering Peking University Shenzhen Graduate School Shenzhen China

ISBN: (纸本)9781467388054

In this paper, a 3D metal-graphene contact with different contact structures (i.e., embedded contact and edge contact) is studied using Kirchhoff model. The influences of some major factors, including metal resistivity, metal-graphene contact resistivity and sheet resistances of graphene both in the channel and under metal, on the total contact resistance are investigated. The sheet resistance of graphene under metal has much more effect on the total contact resistance than other factors. Methods for creating low resistance contact are also proposed.

关键词： Graphene Metals Contact resistance Conductivity Electrodes Resistance Electric potential

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New Insights into the Near-Threshold Design in Nanoscale FinFET Technology for Sub-0.2V Applications

New Insights into the Near-Threshold Design in Nanoscale Fin...

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IEEE International Electron devices Meeting

作者： Xiaobo Jiang Shaofeng Guo Runsheng Wang Yuan Wang Xingsheng Wang Binjie Cheng Asen Asenov Ru Huang Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing 100871 China Synopsys 11 Somerset place Glasgow G3 7JT U.K

ISBN: (纸本)9781509039036

Energy consumption has become the major concern of the IC industry. As a result, near-threshold-voltage (NTV) design has attracted a lot of attention for its superiority in energy efficiency. However, NTV design is faced with the key challenge - variability, especially for FinFET technology where device electrical FoMs are found to be strongly correlated. In this paper, new methodology of NTV design optimization for FinFET is proposed for the first time, and demonstrated based on silicon data. Significant improvements are achieved in the following three aspects: (1) Our newly proposed predictive compact variability models in all-region are accurately calibrated with experimental data, using a simple characterization method;(2) A new efficient approach for logic design space optimization is proposed based on a set of elaborately selected subthreshold FoMs, and the impacts of variation on energy efficiency, delay variation and failure probability are thoroughly investigated;(3) The conventional gate sizing method is also ameliorated specifically for FinFET NTV design. Based on silicon data, the proposed methodology is then demonstrated under V~(dd)=199mV and V_(dd)=145mV, targeting energy-efficiency priority and V_(dd) priority scenarios, respectively. This work provides helpful guidelines for FinFET variation-aware near-threshold design.

关键词： New Insights into Near-Threshold Design FinFET

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A physics-based compact model for material- and operation-oriented switching behaviors of CBRAM

A physics-based compact model for material- and operation-or...

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International Electron devices Meeting (IEDM)

作者： Y. D. Zhao J. J. Hu P. Huang F. Yuan Y. Chai X. Y. Liu J. F. Kang Institute of Microelectronics Peking University Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Innovation Center for MicroNanoelectronics and Integrated System Beijing China Department of Applied Physics The Hong Kong Polytechnic University Hong Kong China

ISBN: (纸本)9781509039036

A physics-based compact model is developed to capture the essential resistive switching behaviors of conductive-bridge random access memory (CBRAM) under DC and AC operations. Three types of evolution modes of conductive filament correlated with material properties and operation schemes are modeled based on experimental observations. By modeling the temperature and electric-field effects as well as the electrical conduction, the model can well reproduce the DC and AC switching characteristics in different material stacks and operation modes. The calibrated model can be further implemented into SPICE to evaluate and optimize the array performance of CBRAM as a device-circuit-system co-design tool.

关键词： Mathematical model Switches Metals Oxidation Geometry Electric fields Data models

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Multi-finger Schottky-Barrier tunneling FET with hybrid operation mechanism for steep transition and high on current

Multi-finger Schottky-Barrier tunneling FET with hybrid oper...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Ru Huang Qianqian Huang Chunlci Wu Jiaxin Wang Cheng Chen Hao Zhu Lingyi Guo Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing

This paper discusses a kind of novel steep-slope switch device, named as multi-finger Schottky-Barrier TFET (MFSB-TFET), with hybrid adaptive operation mechanism, for higher on current, steeper slope as well as low off current. With the on state dominated by Schottky injection current, transition region dominated by band-to-band tunneling and the off current greatly suppressed with increased effective barrier height, the proposed silicon-based MFSB-TFET has experimentally demonstrated low SS, high on current and high on-off current ratio, exhibiting great potentials for ultra-low-power circuit applications.

关键词： Conferences Electron devices Solid state circuits

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A Leakage Tolerant True Single-Phase Clock Dual-Modulus Prescaler Scheme

A Leakage Tolerant True Single-Phase Clock Dual-Modulus Pres...

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Asia-Pacific Microwave Conference

作者： Song Jia Ziyi Wang Shilin Yan Yuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

ISBN: (纸本)9781479987689

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power and area overheads. An HSPICE simulation in a 40 nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable to the performance levels of referenced designs.

关键词： Leakage currents Transistors Performance evaluation Clocks Phase locked loops Robustness Frequency conversion

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