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An adaptive grid algorithm for self-consistent k·p Schrodinger and Poisson equations in UTB InSb-based pMOSFETs

An adaptive grid algorithm for self-consistent k·p Schrodin...

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International Workshop on Computational Electronics

作者： Pengying Chang Xiaoyan Liu Lang Zeng Kangliang Wei Gang Du Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

Hole mobility in ultra-thin body (UTB) InSb-OI devices is calculated by a microscopic approach. An adaptive grid algorithm is employed to discretize 2-D k space. The accurate valence band structures are obtained via solving the 6-band k·p Schrödinger and Poisson equations self-consistently. Hole mobility is computed using the Kubo-Greenwood formalism accounting for nonpolar acoustic and optical phonons, polar optical phonons, and surface roughness scattering mechanisms.

关键词： MOSFET Optical scattering Phonons Silicon Poisson equations Acoustics

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Time dependent 3-D statistical KMC simulation of high-k degradation including trap generation and electron capture/emission dynamic

Time dependent 3-D statistical KMC simulation of high-k degr...

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International Conference on Simulation of Semiconductor Processes and devices (SISPAD)

作者： Yijiao Wang Peng Huang Xiaoyan Liu Gang Du Jinfeng Kang Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

A comprehensive time dependent three dimensional simulation framework for high-k degradation is developed. In this framework, the models that account for trap generation in high-k, capture/emission dynamic, and statistical variability are incorporated in the simulation. The influence of the trap generation model on distribution of traps, threshold voltage, and the amount of trapped charge is investigated in detail, thereby lay a solid foundation for predicting more accurate design margins at circuit/system level in the future.

关键词： Electron traps Logic gates Degradation High K dielectric materials Mathematical model Reliability Hafnium compounds

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A novel CML latch for ultra high speed applications

A novel CML latch for ultra high speed applications

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IEEE Conference on Electron devices and Solid-State circuits

作者： Xuelin Zhang Yuan Wang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781479923366

An ultra high speed current mode logic (CML) latch is proposed in this paper. The latch uses an NMOS transistor controlled by clock signal to improve the tail current of the latching branch, so as to improve the speed of the latch. In 0.13μm CMOS technology, the divide-by-four frequency divider composed of the proposed CML latch can work under the maximum frequency of 15.2GHz, which is almost the twice of the conventional CML latch. Simultaneously, the proposed CML latch consumes only 1.3% more power than the conventional one, realizing a good compromise between speed and power.

关键词： Latches Frequency conversion CMOS integrated circuits Simulation Clocks CMOS technology Frequency division multiplexing

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A SAW-less 0.5–2.5 GHz receiver front-end with 80 dB 3rd order harmonic rejection ratio

A SAW-less 0.5–2.5 GHz receiver front-end with 80 dB 3rd or...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Long Chen Tao Xia Ying Guo Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

ISBN: (纸本)9781479934331

This paper presents a 65 nm SAW-less receiver front-end. Using 3-phase clocks for impedance translation, an RF filter with 3 rd order harmonic rejection is obtained. Employing this filter as the front-end's input matching network and a two-stage low noise amplifier's load, a 3 rd order RF filter is realized. In addition, by using 3-phase 1/3-duty-cycle LO, a 3 rd order harmonic rejection mixer is realized. The mixer's harmonic rejection ratio is less sensitive to gain and phase error compared to conventional 8-phase mixers, since the 3-path's gain ratio is 1:2:1. These two techniques enhance 3 rd order harmonic rejection ratio to 80 dB in case of 6% duty-cycle error, 2% gain error and 0.5° phase error. The front-end achieves a noise figure of 3-6 dB from 0.5 GHz to 2.5 GHz, consumes 21-33 mW power from a 1.2 V voltage supply and occupies an area of 0.35 mm 2 .

关键词： Gain Power harmonic filters Mixers Harmonic analysis Impedance Radio frequency Band-pass filters

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A clock calibration method for an all-digital burst-mode CDR with embedded TDC

A clock calibration method for an all-digital burst-mode CDR...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Baoguang Liu Yuan Wang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781479923366

This paper presents a novel calibration method for an all-digital burst-mode clock and data recovery (BM-CDR) with embedded time-to-digital converter (TDC). The proposed method ensures the TDC-embedded Phase Generator to get the precise delays outside of Shared Delay Line, which makes the measured period more exactly. This method operates at 1.25Gbps. Compared with the BM-CDR without calibration, the proposed method reduces the clock jitter from 221.58ps to 98.11ps, about 55.72% under a 5-bit consecutive identical digits.

关键词： Clocks Image edge detection Generators

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An improved CMOS ring oscillator PLL applied in RapidIO communications

An improved CMOS ring oscillator PLL applied in RapidIO comm...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Shanliang Gan Yuan Wang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781479923366

A low jitter CMOS ring oscillator phase-locked loop (PLL) is presented in this paper. An improved voltage controlled oscillator (VCO) frequency control method is applied, and additional charge pump switches are used in the designed PLL. The VCO phase noise is -118.65dBc/Hz at 1 MHz offset from 3.125 GHz carrier, and the PLL total output jitter is 1.16ps at 3.125GHz in GlobalFoundries 0.13μm CMOS technology. The PLL locking time is 8μs and the total power dissipation with IO is 9.3mW.

关键词： Voltage-controlled oscillators CMOS integrated circuits Clocks Control systems Frequency control CMOS technology Phase frequency detector

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Hole mobility in InSb-based devices: Dependency on surface orientation, body thickness and strain

Hole mobility in InSb-based devices: Dependency on surface o...

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European Conference on Solid-State Device Research (ESSDERC)

作者： Pengying Chang Lang Zeng Xiaoyan Liu Gang Du Key Laboratory of Microelectronic Devices and Circuits (MOE) Peking University Beijing China

This work presents an investigation on hole mobility in InSb-based ultra-thin body (UTB) devices with arbitrary surface orientation, body thickness and biaxial strain. The anisotropic band structures with quantum confinement are computed using a fully self-consistent solver for six-band k·p Schrödinger and Poisson equations. Hole mobility is computed using the Kubo-Greenwood formalism accounting for nonpolar acoustic and optical phonons, polar optical phonons and surface roughness scattering. The models are calibrated by fitting the experimental data. Our results suggest that for T B (111)>(110)/[001]>(001), where devices with (111) have more excellent behavior than for Si. In addition, biaxial compressive strain introduces maximum mobility gain in the (110)/[110] case. Nevertheless, (110)/[110] is the optimal surface and channel direction for InSb-based UTB devices, followed by (111) orientation.

关键词： Strain Scattering Phonons Silicon Effective mass MOSFET Rough surfaces

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A 6.25Gb/s CMOS clock and data recovery DLL with anti-harmonic lock

A 6.25Gb/s CMOS clock and data recovery DLL with anti-harmon...

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IEEE Conference on Electron devices and Solid-State circuits

作者： Yuequan Liu Yuan Wang Song Jia Ganggang Zhang Xing Zhang Key Laboratory of Microelectronic Devices and Circuits (MoE) Peking University Beijing China

ISBN: (纸本)9781479923366

This paper presents a clock and data recovery (CDR) delay locked loop that operates in high frequency while keeping low jitter performance. The data rate can be twice the reference clock frequency. A self-starting-control circuit widens the phase capture range. In order to compensate for the attenuation of channel, an equalizer comprised of two peaking amplifiers is employed in front end of CDR. The circuit is implemented in SMIC 1.2V 65nm CMOS technology. It demonstrates that at 6.25Gb/s data with -20dB attenuation, the periodic jitter of the recovery clock is 14.08ps for a total power consumption of 6.5mW.

关键词： CMOS integrated circuits CMOS technology Clocks

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An efficient test structure for interface trap characterization under BTI stresses

An efficient test structure for interface trap characterizat...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Yandong He Ganggang Zhang Lin Han Xing Zhang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing CHINA

ISBN: (纸本)9781479932849

An efficient test structure for interface trap density characterization has been proposed. Based on this single structure and one-time IV measurement, the interface trap densities on both n- and p-type Si/SiO 2 interfaces are obtained, achieving 1x efficiency improvement and 50% cost reduction. BTI-stress-induced degradation was studied and compared under the same structure, demonstrating a better test efficiency and resolution to interface traps generation at different Si/SiO 2 interfaces.

关键词： Logic gates Current measurement Area measurement Abstracts Performance evaluation Substrates Reliability

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A comprehensive NBTI degradation model based on ring oscillator circuit

A comprehensive NBTI degradation model based on ring oscilla...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Fang Qiao Yandong He Leilei Ai Ganggang Zhang Xing Zhang Key Laboratory -of Microelectronic Devices and Circuits Peking University Beijing CHINA Peking University Beijing Beijing CN

ISBN: (纸本)9781479932849

Negative bias temperature instability (NBTI) as one of CMOS device degradations has been extensively researched. Based on the theories of NBTI degradations, we optimize a reliability model for the frequency degradation of the ring oscillator (RO), and propose a new ring oscillator structure corresponding to the model. In this paper, the new ring oscillator is working under two different static stress modes. We found that the frequency degradation of the same RO is much different in different static stress modes, and the degree of the frequency degradation of different-stage ROs shows the same trend in different stress modes. The model is demonstrated by using the SMIC 65nm, 1.2V technology.

关键词： Degradation Oscillators Abstracts Digital signal processing Stress Market research

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