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Valence band variation in Si(110) nanowire induced by a covered insulator

Chinese Physics B 2010年第1期19卷 398-402页

作者：许洪华刘晓彦何毓辉樊春杜刚孙爱东韩汝琦康晋锋 Institute of Microelectronics Peking University & Key Laboratory of Microelectronic Devices and CircuitsMinistry of Education Computer Center of Peking University

In this work, we investigate strain effects induced by the deposition of gate dielectrics on the valence band structures in Si （110） nanowire via the simulation of strain distribution and the calculation of a generalized 6 × 6k .p strained valence band. The nanowire is surrounded by the gate dielectric. Our simulation indicates that the strain of the amorphous SiO2 insulator is negligible without considering temperature factors. On the other hand, the thermal residual strain in a nanowire with amorphous SiO2 insulator which has negligible lattice misfit strain pushes the valence subbands upwards by chemical vapour deposition and downwards by thermal oxidation treatment. In contrast with the strain of the amorphous SiO2 insulator, the strain of the HfO2 gate insulator in Si （110） nanowire pushes the valence subbands upwards remarkably. The thermal residual strain by HfO2 insulator contributes to the up-shifting tendency. Our simulation results for valence band shifting and warping in Si nanowires can provide useful guidance for further nanowire device design.

关键词： silicon nanowire valence band thermal residual strain

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Oxide-based RRAM: Unified microscopic principle for both unipolar and bipolar switching

Oxide-based RRAM: Unified microscopic principle for both uni...

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International Electron devices Meeting (IEDM)

作者： B. Gao J. F. Kang Y. S. Chen F. F. Zhang B. Chen P. Huang L. F. Liu X. Y. Liu Y. Y. Wang X. A. Tran Z. R. Wang H. Y. Yu Albert Chin Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Peking University Beijing China School of EEE Nanyang Technological University Singapore Singapore Department of Electronics Engineering National Chiao-Tung University Hsinchu Taiwan

A unified microscopic principle is proposed to clarify resistive switching behaviors of transition metal oxide based resistive random access memories (RRAM) for the first time. In this unified microscopic principle, both unipolar and bipolar switching characteristics of RRAM are correlated with the distribution of localized oxygen vacancies in the oxide switching layer, which is governed by the generation and recombination with dissociative oxygen ions. Based on the proposed microscopic principle, an atomistic simulation method is developed to evaluate critical memory performance, and successfully conduct the device optimization. The experimental data are well in line with the developed simulation method.

关键词： Switches Voltage measurement Resistance Mathematical model Microscopy Hafnium oxide

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Two effective single-loop high-performance sigma-delta modulators based on 0.13μm CMOS

Two effective single-loop high-performance sigma-delta modul...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Li, Hongyi Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424457984

In this paper, two high-resolution mediumbandwidth single-loop 4 th-order single-bit sigma-delta modulators using a feed-forward and a feedback topology respectively are implemented in 0.13μm CMOS technology. The oversampling ratio is 50 with 312.5kHz input bandwidth, 14.66-bit and 16.62-bit resolution have been reached. The two circuits each consume about 8-mW from a single 1.2V supply voltage. After simulation, under the same circuit conditions, feedback structure gives better performance than feed-forward one. The experiment result could be a useful reference for the topology choice. ©2010 IEEE.

关键词： CMOS integrated circuits

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A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic linearity

A 14-bit 300MHz pipelined DEM DAC with enhanced dynamic line...

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2nd Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Junlei, Zhao Yuan, Wang Zhihui, Zhao Song, Jia Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424467372

This paper presents a 14-bit digital-to-analog converter (DAC) with pipelined dynamic element matching to eliminate signal-dependent distortions and achieve good linearity at high sampling frequencies. A return-to-zero output stage is developed to enhance the dynamic linearity and increase the output impedance of current sources. And a novel current source array is employed to eliminate systematic and graded errors. The spurious-free dynamic range is 80.9dB at 312MS/s with a 150MHz input. The DAC is implemented in a 0.13-μm CMOS process, and consumes 48mW at 1.2-V power supply and 312MS/s.

关键词： Digital to analog conversion

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A clock and data recovery circuit for 3.125Gb/s RapidIO SerDes

A clock and data recovery circuit for 3.125Gb/s RapidIO SerD...

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2010 IEEE International Conference of Electron devices and Solid-State circuits, EDSSC 2010

作者： Zhihui, Zhao Yuan, Wang Junlei, Zhao Hailing, Yang Song, Jia Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424499977

This work presents a low-power low-cost CDR design for RapidIO SerDes. The design is based on phase interpolator, which is controlled by a synthesized standard cell digital block. Half-rate architecture is adopted to lessen the problems in routing high speed clocks and reduce power. An improved half-rate bang-bang phase detector is presented to assure the stability of the system. Moreover, the paper proposes a simplified control scheme for the phase interpolator to further reduce power and cost. The CDR takes an area of less than 0.05mm2, and post simulation shows that the CDR has a RMS jitter of UIpp/32 (11.4ps@3.125GBaud) and consumes 9.5mW at 3.125GBaud. © 2010 IEEE.

关键词： Clocks

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Improved multi-loop SMASH sigma-delta modulator for wideband applications

Improved multi-loop SMASH sigma-delta modulator for wideband...

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2010 IEEE International Conference of Electron devices and Solid-State circuits, EDSSC 2010

作者： Li, Hongyi Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424499977

In this paper, a novel design method has been proposed to realize feed-forward low-distortion unity STF sigma-delta modulators which are the critical blocks in multi-loop SMASH structure. Using the method, a timing-relaxed stable unity STF 2nd-order modulator has been proposed in detail. After that, an extremely high-resolution SMASH 2(3b)-2(3b)-1(2b) has been suggested using the proposed stages. Extensive results prove the efficiency of this topology. © 2010 IEEE.

关键词： Modulators

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Cascade 2-2 sigma-delta modulators for wideband high-resolution applications

Cascade 2-2 sigma-delta modulators for wideband high-resolut...

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2nd Asia Pacific Conference on Postgraduate Research in microelectronics and Electronics, PrimeAsia 2010

作者： Li, Hongyi Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices Circuits Institute of Microelectronics Peking University Beijing China

ISBN: (纸本)9781424467372

In this paper, several techniques which relax circuit requirements of building blocks are presented to effectively realize wideband high-resolution cascade sigma-delta modulator. Three cascade structures have been proposed in this paper. First, a MASH 2-2 with feed-forward topology in both stages has been explained to obtain low-distortion property and remove subtraction. Second, a flexible SMASH 2-2 has been proposed to choose appropriate coefficients for different requirements. Third, a SMASH 2-2 with feed-forward quantization noise self-coupled structure has been displayed to cancel quantization error of the preceding stage totally. Detailed simulation results and comparisons demonstrate the performance of these topologies.

关键词： Topology

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Predictive modeling of capacitance and resistance in gate-all-around cylindrical nanowire MOSFETs for parasitic design optimization

Predictive modeling of capacitance and resistance in gate-al...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Xu, Qiumin Zou, Jibin Luo, Jieyin Wang, Runsheng Huang, Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457984

This paper presents a predictive electrostatic capacitance and resistance compact model of multiple gate MOSFET with cylindrical conducting channels, taking into account parasitic effects, quantum confinement and quasi-ballistic effects. The model incorporates the dependence of channel length, gate height and width, gate-to-contact spacing, nanowire size, multiple channels, as well as 1-D ultra-narrow source/drain extension (SDE) doping profile. The proposed non-iterative electrostatic model is successfully verified, and can be used to predict nanowire-based circuit performance. Based on the analytical model, we can further examine which parasitic components are affecting the delay. Results revealed that Cside, Cof, Rsd, RQ are dominant factors and should be treated as a major design concern. Among all the parameters, Lsd, Tg and Ndop are essentially important in parasitic design optimization. By selectively modifying these parameters, parasitic effect is evidently reduced. ©2010 IEEE.

关键词： Nanowires

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Study of LDMOS-SCR: A high voltage ESD protection device

Study of LDMOS-SCR: A high voltage ESD protection device

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Zhang, Peng Wang, Yuan Jia, Song Zhang, Xing Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

A novel LDMOS-SCR device for electrostatic discharge protection of power device is presented. The device is able to be fabricated in SOI 40V LDMOS process without any extra mask. Due to the new structure, a proper and... 详细信息

ISBN: (纸本)9781424457984

关键词： Electrostatic devices

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Impacts of diameter-dependent annealing on S/D extension random dopant fluctuations in silicon nanowire MOSFETs

Impacts of diameter-dependent annealing on S/D extension ran...

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2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology

作者： Yu, Tao Wang, Runsheng Ding, Wei Huang, Ru Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424457984

In this paper, the impacts of diameter-dependent annealing (DDA) effect on nanowire S/D extension random dopant fluctuations (SDE-RDF) in silicon nanowire MOSFETs (SNWTs) are investigated, in terms of electrostatic properties, source/drain series resistance (RSD), and driving current. The SDE-RDF induced variations of threshold voltage (Vth) and DIBL in SNWTs with different diameters are found to be modest and decrease as the diameters down-scale. However, SDE-RDF induced RSD variation in SNWTs is enhanced by abnormal DDA effects, which aggravates the drive current variations with the downscaling of SNWT diameter. The results also show that Vth is the dominant factor in ON/OFF current ratio variation while RSD dominates that of ON current. The tradeoff between RSD and Vth dominant current variations is discussed to give some guidelines for SDE-RDF-aware design in SNWTs. ©2010 IEEE.

关键词： Threshold voltage

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