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A VCO sub-band selection circuit for fast PLL calibration

Journal of Semiconductors 2009年第8期30卷 153-155页

作者：宋颖王源贾嵩赵宝瑛 Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

A novel voltage controlled oscillator （VCO） sub-band selection circuit to achieve fast phase locked loop （PLL） calibration is presented, which reduces the calibration time by measuring the period difference directly and accomplishing an efficient search for an optimum VCO sub-band. The sub-band selection circuit was implemented in a 0.18 μm CMOS logic process with a PLL using an 8 sub-band VCO. The measured calibration time is less than 3 μs in a VCO frequency range from 600 MHz to 2 GHz. The proposed circuit consumes 0.64 mA at most.

关键词： PLL VCO calibration

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Influence of boundary force on the performance of gate-all-around Ge (110) NW FETs with HfO2 gate insulator

Influence of boundary force on the performance of gate-all-a...

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IEEE International Nanoelectronics Conference (INEC)

作者： Honghua Xu Xiaoyan Liu Gang Du Yuhui He Chun Fan Ruqi Han Jinfeng Kang Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Ministry of Education Peking University Beijing China Institute of Microelectronics Peking University Beijing China Key Laboratory of Nanofabrication and Novel Devices Integration Technology Institute of Microelectronics Chinese Academy and Sciences Beijing China Computer Center Peking University Beijing China

ISBN: (纸本)9781424435432;9781424435449

We calculate valence band structures and transport property of HfO 2 gate dielectric surrounded Ge (110) nanowire with a radial force at the boundary of the insulator. The radial force pushes the valence subbands downwards. Most of hole effective masses of top five subbands decrease and densities of states' peaks move down as the force increases. The hole mobility in Ge (110) NW significantly increases with higher force values.

关键词： FETs Hafnium oxide Dielectrics and electrical insulation Capacitive sensors Effective mass Nanoscale devices Electrodes Lattices Voltage High-K gate dielectrics

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Design and test results of a readout circuit for high energy particle detectors

Design and test results of a readout circuit for high energy...

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International Symposium on Photoelectronic Detection and Imaging 2009: Terahertz and High Energy Radiation Detection Technologies and Applications

作者： Zhang, Mingming Chen, Zhongjian Zhang, Yacong Lu, Wengao An, Huiyao Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University China

ISBN: (纸本)9780819476661

A readout integrated circuit for high energy particle detectors is presented. The circuit designed is composed of a Charge Sensitive Amplifier (CSA), a pulse shaper with four selectable peaking time, and an output stage. The readout circuit has been designed in a 0.35um DPTM CMOS technology and tested with Verigy 93000. The size of readout circuit is 1.7*0.7mm 2. The power supply voltage is 5V. The average gain is about 20.5mV/fC and the Equivalent Noise Charge (ENC) with detector disconnected is 550-650e for five chips in the typical mode. The power dissipation is about 8mW and 2mW respectively, with and without output buffer. The linearity reaches 99.2% in the typical mode. The gain is tunable from 13mV/fC to 130mV/fC and the peaking time varies from 700ns to 1.6us. © 2009 SPIE.

关键词： Timing circuits

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A Monte Carlo study of ambipolar Schottky barrier MOSFETs

A Monte Carlo study of ambipolar Schottky barrier MOSFETs

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2009 13th International Workshop on Computational Electronics, IWCE 2009

作者： Lang, Zeng Xiao, Yan Liu Gang, Du Jin, Feng Kang Ru, Qi Han Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9781424439270

In this paper, we demonstrate a Monte Carlo simulator for ambipolar Schottky barrier MOSFETs which includes tunneling and thermal emission of electrons and holes and the appropriate treatment of carrier transport at nano-scale. The ambipolar characteristic of SB MOSFETs is reproduced by this simulator. The four operation modes in both n and p SB MOSFETs are revealed. Based on these simulations, it is summarized that the tunneling at source side dominates the carrier transport. ©2009 IEEE.

关键词： Schottky barrier diodes

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Design of readout circuit for microcantilever infrared focal plane array with snapshot integration

Design of readout circuit for microcantilever infrared focal...

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International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications

作者： Lei, Ke Chen, Zhongjian Cao, Junmin Zhang, Yaciong Lu, Wengao Ji, Lijiu Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University 100871 China

ISBN: (纸本)9780819476647

Design of a CMOS readout circuit for 160x120 format microcantilever infrared FPAs with snapshot integration is presented in this paper. The pixel pitch is 50m and capacitive trans-impedance amplifier is used in pixel stage for low noise and high linearity. A 800fF storage capacitor is implemented in each pixel for snapshot imaging. The pixel OTAs are powered off during pixel signals readout phase and master-slave buffer method is employed in column readout stage and output buffer stage for low power. The 160x120 ROIC has been designed and simulated for 50Hz frame frequency with one output port. The pixel rate is 1MHz, charge handling capacity is 1.5x105 electrons, pixel linearity is as high as 99.9% and the power consumption is less than 20mw. A 16x16 experimental chip has been designed, post-simulated and manufactured with a 0.35m CMOS DPTM technology and is being tested. © 2009 SPIE.

关键词： Pixels

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Design of readout circuit for microcantilever-based ripple uncooled infrared focal plane arrays

Design of readout circuit for microcantilever-based ripple u...

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International Symposium on Photoelectronic Detection and Imaging 2009: Advances in Infrared Imaging and Applications

作者： Cao, Junmin Chen, Zhongjian Lu, Wengao Zhang, Yacong Lei, Ke Zhao, Baoying Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9780819476647

A readout integrated circuit (ROIC) for uncooled microcantilever infrared focal plane arrays (IRFPAs) based on capacitive readout is proposed. The ROIC is optimized according to noise modeling and analysis to reduce noise. An experimental chip of 1616 FPAs readout circuit has been designed and fabricated using 0.35um CMOS technology. The measurement results showed that the power dissipation is 16.5mW from a 5V supply voltage at 50Hz frame rate, the linearity is 99.2% at the typical mode;the uniformity is larger than 97% and the equivalent noise charge (ENC) is below 150e. It is believed that the ROIC has a great potential in the applications of large-scale micro-cantilever-based uncooled IRFPAs. © 2009 SPIE.

关键词： Timing circuits

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A comparative study of double gate mosfet with asymmetric barrier heights at source/drain and the symmetric DG-SBFET

A comparative study of double gate mosfet with asymmetric ba...

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9th International Workshop on Junction Technology, IWJT 2009

作者： Du, Xiong-Xiong Sun, Lei Liu, Xiao-Yan Han, Ru-Qi Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing 100871 China

ISBN: (纸本)9781424439447

Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are simulated. A comparative study between them is made. We have found that the DG-ASBFET is more appropriate for LOP and LSPT applications. Furthermore, the DG-ASBFET shows a better scale ability and better immunity to the short channel effects. ©2009 IEEE.

关键词： MOSFET devices

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The Combined Impact of Total Ionizing Dose Effect and Negative Bias Temperature Stress on Deep Sub-Micron pMOSFETs

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ECS Transactions 2010年第1期27卷

作者： Jian Wang Wenhua Wang Detao Huang Shoubin Xue Sihao Wang Wen Liu Ru Huang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University No. 5 Yiheyuan Road Beijing Beijing 100871 China Institute of Microelectronics Peking University

In this paper, we investigate the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) on deep sub-micron pMOSFETs. It is found that the high temperature of the NBT stress induces an annealing effect by removing part of the radiation-induced positive charges. If we choose a relatively low temperature to avoid the annealing effect, a remarkable radiation acceleration effect on device degradation is observed and the lifetime of pMOSFETs significantly reduces due to more radiation-induced new hole traps in the oxide. However, the acceleration effect seems independent of the oxide electric field during NBT stress. The work in this paper indicates that it is important to choose proper NBT stress conditions if we use NBTI to predict the lifetime of the pMOSFETs which operate in the radiation environments.

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Investigation of Different Strain Configurations in Gate-All-Around Silicon Nanowire Transistor

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ECS Transactions 2010年第1期27卷

作者： Quanxin Yun Jing Zhuge Ru Huang Runsheng Wang Xia An Liangliang Zhang Xing Zhang Yangyuan Wang Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University NO.5 Yiheyuan Road Haidian District Beijing Beijing 100871 China Institute of Microelectronics Peking University

The impacts of three different strain configurations on both DC and RF performance of n-type silicon nanowire transistors (n-SNWTs) are investigated. It is found that the longitudinal tensile strain is the most efficient in improving the driving current and RF performance of n-SNWTs under the same stress value. In addition, the transverse compressive strain is also beneficial to the performance improvement, and can be combined in the stress engineering. Particularly, transverse biaxial compressive strain can effectively enhance the driving current, and at the same time slightly decrease the off-current of n-SNWT, which is beneficial for high speed and low power design. The results indicate that, due to the unique feature of gate-all-around 1D structure, the strain design in SNWTs, especially the combination of longitudinal strain and transverse strain, can be specially optimized for better device performance.

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Radial boundary forces-modulated valence band structure of Ge (110) nanowire

Radial boundary forces-modulated valence band structure of G...

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2009 13th International Workshop on Computational Electronics, IWCE 2009

作者： Honghua, Xu Yuhui, He Yuning, Zhao Gang, Du Jinfeng, Kang Ruqi, Han Xiaoyan, Liu Chun, Fan Institute of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China Computer Center of Peking University Beijing China

ISBN: (纸本)9781424439270

For the radial boundary force induced in the process, the strain energy distribution and strain tensor components in Ge (110) nanowire (NW) are calculated by finite element method. Based on the strain distribution, we compute valence band structures with different radial forces. As increasing force values, top valence subbands shift downwards. The influence on the corresponding effective masses and density of states are also investigated. ©2009 IEEE.

关键词： Nanowires

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