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A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability

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Science China(Information Sciences) 2020年第2期63卷 245-247页

作者： Yang ZHAO Qianqian HUANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University

Dear editor,As CMOS technology scaling down, the reduction of supply voltage and power consumption becomes extremely difficult due to the subthreshold swing(SS) limitation (60 m V/dec) at room *** FET (TFET) with band-to-band tunneling (BTBT) mechanism is regarded as one of the most promising emerging low-power devices due to its sub-60 m V/dec SS and ultra-low off-current

关键词： A novel tunnel FET design through hybrid modulation with optimized subthreshold characteristics and high drive capability FET

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A 20-Gb/s Low Power Inductorless TIA Design in 0.18µm CMOS

A 20-Gb/s Low Power Inductorless TIA Design in 0.18µm CMOS

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International Conference on Electronic Engineering and Informatics (EEI)

作者： Zhiwei Zeng Weilin Xu Peisi Mo Haiou Li Education Department of Guangxi Zhuang Autonomous Region Key Laboratory of Microelectronic Devices and Integrated Circuits Guilin University of Electronic Technology Guilin China Guangxi Key Laboratory of Precision Navigation Technology and Applications Guilin University of Electronic Technology Guilin China

ISBN: (数字)9798350353594

ISBN: (纸本)9798350353600

The performance demands on transimpedance amplifiers (TIA) for optoelectronic conversion have increased with the rapid development of fiber optic communication technology. A modified feedforward common gate (MFCG) transimpedance amplifier with an inductor less topology is suggested for analogue front-end wireless fiber optic communications applications. This leads to a significant improvement in the circuit power consumption and band-width. An improved auxiliary amplifier without Miller effect is used instead of the traditional FCG common source amplifier to improve the bandwidth and reduce the phase jitter. An improved parallel active inductor is used instead of the traditional active inductor to obtain a more favorable bandwidth compensation effect. Small-signal analysis demonstrated that the M-FCG has a low input impedance, a large output impedance and transconductance con-version ratio. Based on a 0.18-µm CMOS process post-simulation results, the M-FCG circuit exhibits a transimpedance gain of 58.87 dBΩ, a bandwidth of 6.33 GHz, an equivalent input current noise of 27.02 pA/-VHz, a power consumption of 1.9 mW in the core circuit, and occupies a layout area of 0.0054 mm2. Additionally, the eye diagrams were generated using PRBS at a rate of 20 Gb/s. The resulting eye diagram displays openness and clarity, thereby meeting the requirement for 20 Gb/s code element transmission.

关键词： Optical fiber amplifiers Wireless communication Power demand Active inductors Codes Noise Bandwidth Logic gates Impedance Transconductance

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Experimental Investigation of Ultra-Low Temperature LA2O3/HFO2Bi-Layer Dipole-First Process Using PVD Method for Advanced IC Technology

Experimental Investigation of Ultra-Low Temperature LA2O3/HF...

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2023 China Semiconductor Technology International Conference, CSTIC 2023

作者： Wei, Yanzhao Yao, Jiaxin Xu, Renren Zhang, Qingzhu Yin, Huaxiang Chinese Academy of Sciences Integrated Circuit Advanced Process R&d Center Institute of Microelectronics Beijing100029 China Institute of Microelectronics Chinese Academy of Sciences Key Laboratory of Microelectronic Devices and Integrated Technology Beijing100029 China University of Chinese Academy of Sciences School of Integrated Circuits Beijing100049 China

ISBN: (纸本)9798350311006

In this paper, a La2O3/HfO2 bi-layer dipole-first (DF) process is proposed and investigated by ultra-low temperature PVD dielectric laminates to achieve lower gate effective work function (EWF) for monolithic 3D-IC (M3D) application. The impacts of ultra-low temperature La-dipole on EWF modulation and interfacial properties are comprehensively investigated. It is found that the flat-band voltage (VFB) negatively shifts 60 mV with sub-1nm La2O3 thickness, which provides an effective way to meet the require of Si conduction band-edge EWF modulation. Furthermore, the electron trap/detrap densities (Not) and interfacial trap densities (Dit) are suppressed by La2O3/HfO2 bi-layer DF process to improve device performance. These results exhibit a promising bi-layer DF process in low thermal integration for advanced IC technology. © 2023 IEEE.

关键词： Timing circuits

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Experimental Demonstration of A CT-FeFET Array with Intrinsic Long-Short-Term Plasticity for Low-Cost Trajectory Prediction

Experimental Demonstration of A CT-FeFET Array with Intrinsi...

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International Electron devices Meeting (IEDM)

作者： Chao Li Jie Yu Xumeng Zhang Zhaohao Zhang Fangduo Zhu Siyuan Ouyang Pei Chen Lingli Cheng Gaobo Xu Qingzhu Zhang Huaxiang Yin Qi Liu Ming Liu State Key Laboratory of Integrated Chips and Systems Frontier Institute of Chip and System Fudan University Shanghai China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing China Key Laboratory of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Beijing China

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

Trajectory prediction is a vital function in the auto-driving field, typically achieved with a long short-term memory network. Static IMC technology accelerates the computing of long-term parameters, while the execution of short-term parameters faces great buffer overhead. Inspired by the fused long-short-term synaptic plasticity in biology, here, we proposed a dynamic IMC strategy based on a charge-trapping FeFET array with intrinsic long-short-term plasticity. The long-term weights are stored in the ferroelectric domain, while the short-term weights are in-situ dynamically operated in a charge-trapping domain, eliminating the external caching process. We further demonstrated a dynamic IMC neuromorphic system built on this array for performing trajectory prediction of moving vehicles, achieving more than 1000x and 4x improvements than GPU in power consumption and memory overhead.

关键词： Performance evaluation Power demand Neuromorphics Memory management Graphics processing units Trajectory Vehicle dynamics Synapses Long short term memory FeFETs

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On-Chip Incremental Learning based on Unsupervised STDP Implementation

On-Chip Incremental Learning based on Unsupervised STDP Impl...

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IEEE International Conference on Artificial Intelligence circuits and Systems (AICAS)

作者： Guang Chen Jian Cao Shuo Feng Zilin Wang Yi Zhong Qibin Li Xiongbo Zhao Xing Zhang Yuan Wang School of Software and Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits (MoE) MPW Center Peking University Beijing China School of Integrated Circuits Peking University Beijing China Beijing Aerospace Automatic Control Institute Beijing China

ISBN: (数字)9798350383638

ISBN: (纸本)9798350383645

Spiking neural network (SNN), a bio-inspired neuron network, utilizes a learning rule named spike-timing-dependent plasticity (STDP) to achieve high-performance unsupervised learning. However, it may suffer from catastrophic forgetting when the distribution of new data significantly differs from that of old data. To address this issue, an incremental learning implementation for ship classification is presented in this paper. We develop an incremental learning algorithm based on STDP and corresponding platform. A competitive SNN is built into our algorithm, and add-STDP is utilized to update the weights of network for efficient learning. To enhance learning performance, we incorporate weight decay. And to avoid catastrophic forgetting, we incorporate data replay. The corresponding learning platform consists of the FPGA Zynq 7100 and the STDP neuromorphic prototype chip, and our algorithm is executed on the chip. We evaluate the ship classification task on our platform, which demonstrates the superior potential of our on-chip implementation for incremental learning.

关键词： Incremental learning Neuromorphics Neurons Prototypes Spiking neural networks Classification algorithms System-on-chip

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A High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD Array 15

A High Dynamic Range Pixel Circuit with High-voltage Protect...

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15th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2020

作者： Gu, Yuting Lu, Wengao Niu, Yuze Zhang, Yacong Chen, Zhongjian Key Laboratory of Microelectronic Devices and Circuits Peking University Department of Microelectronics China

ISBN: (纸本)9781728162355

This paper presents a high dynamic range pixel circuit with high-voltage protection for 128×128 Linear-mode avalanche photodiode (LM-APD) array. The pixel circuit includes a high-voltage transistor, a pixel-level analog-to-digital converter (ADC), and a high-voltage protection circuit based on circuit-shared. Through circuit-shared, the pixel-level A/D conversion and high-voltage protection are completed efficiently. Meanwhile, the dynamic range of the entire circuit is greatly improved. The chip is designed in 0.18µm CMOS process. The frame rate is 100Hz and the resolution is 16bit. The simulation results indicate that the dynamic range is 94dB and the power consumption is 5µW per pixel. The pixel pitch is 100µm, which can be reduced further with smaller APD detector. © 2020 IEEE.

关键词： Surge protection

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Demonstration of Planar Geometry PIN Photodetectors with GeSi/Ge Multiple Quantum Wells Hybrid Intrinsic Region on a Ge-on-Insulator Platform

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ACS Applied Electronic Materials 2025年第11期7卷 5205-5216页

作者： Junhao Du Xuewei Zhao Yuanhao Miao Jiale Su Ben Li Xiangliang Duan Tianyu Dong Jiahan Yu Hongxiao Lin Yuhui Ren Bo Wang Tianchun Ye Henry H. Radamson Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China；School of Integrated Circuits University of Chinese Academy of Sciences Beijing 100049 China Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou 510535 China Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China；Research and Development Center of Optoelectronic Hybrid IC Guangdong Greater Bay Area Institute of Integrated Circuit and System Guangzhou 510535 China；School of Integrated Circuits University of Chinese Academy of Sciences Beijing 100049 China

In this article, the first demonstration of planar geometry Ge PIN short-wave infrared (SWIR) photodetectors (PDs) on a germanium-on-insulator (GOI) platform has been presented. The intrinsic layer Ge contains four Ge0.86Si0.14multiple quantum wells (MQWs). The structural characteristics, material quality, and interface integrity of the PDs were investigated by using high-resolution transmission electron microscopy (HR-TEM) and high-resolution X-ray diffraction (HR-XRD). The devices exhibited a 3.12 mA/cm2dark current density and a low bulk leakage current density of 0.94 mA/cm2at −1 V. The integration of tensile-strained GeSi/Ge MQWs significantly enhanced the responsivity while maintaining a relatively lower dark current density, thereby broadening the spectral response range to 1700 nm. The notably high responsivities at 1310 and 1550 nm are 0.99 and 0.78 A/W, respectively, corresponding to external quantum efficiencies (EQEs) of 93.7 and 62.4%. Furthermore, the optical confinement effect inherent to this type of GOI structure contributed to a pronounced enhancement in the responsivity across the O, E, S, and C bands, with a peak responsivity of 1.11 A/W at 1475 nm. These findings underscore the potential of CMOS-compatible GOI platforms with MQWs hybrid intrinsic regions for diversified optoelectronic applications. Additionally, the demonstrated planar geometry Ge PIN PDs on insulator substrates exhibit excellent prospects for high-resolution SWIR imaging, which pave the way for advancements in next-generation photonic and sensing technologies.

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Low power and high uniformity of HfOx-based RRAM via tip-enhanced electric fields

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Science China(Information Sciences) 2019年第10期62卷 164-170页

作者： Xiaokang LI Baotong ZHANG Bowen WANG Xiaoyan XU Yuancheng YANG Shuang SUN Qifeng CAI Shijie HU Xia AN Ming LI Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University

In this paper, the HfOx-based resistive random access memory（RRAM） devices with sub-100 nm pyramid-type electrodes were fabricated. With the help of tip-enhanced electric field around the pyramid-type electrodes, it was experimentally demonstrated that the novel devices have better cycle-to-cycle variation control, lower forming/set voltage（1.97/0.7V） and faster switching speed（≤30 ns under 0.9V pulse） as well as better endurance reliability than conventional flat electrode resistive memory devices. In addition,the novel RRAM is experimentally demonstrated with independence of electrode number for the first time to present great potential in scaling down. This novel structure metal-oxide based RRAM will be suitable for the future low-power non-volatile memory application.

关键词： RRAM pyramid-type electrode variation reliability switching speed conducting filament

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Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection

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Science China(Information Sciences) 2019年第6期62卷 79-86页

作者： Lizhong ZHANG Yuan WANG Yize WANG Xing ZHANG YANDong HE Key Laboratory of Microelectronic Devices and Circuits (MoE) Institute of MicroelectronicsPeking University

A conventional diode-triggered silicon-controlled rectifier(DTSCR) structure with a layout strategy for electrostatic discharge(ESD) protection is presented and confirmed in a 65-nm CMOS *** modified device is featured by a scaled-down trigger-diode string, which shortens its turn-on time using a variable scaling factor. To confirm the parasitic resistance adjustments of the modified DTSCR, transmission line pulsing(TLP)/very fast transmission line pulsing(VF-TLP) tests and simulations are performed on the device. Compared to a conventional DTSCR, this structure exhibits an improved turn-on speed and robustness, which are suitable for I/O protection of ESD events in the nanosecond range, particularly the charged-device model(CDM) event.

关键词： diode triggered silicon controlled rectifier(DTSCR) electrostatic discharge(ESD) transmission line pulsing(TLP) very fast transmission line pulsing(VF-TLP) turn-on behavior

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A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor

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Science China(Information Sciences) 2020年第6期63卷 253-255页

作者： Gong CHEN Bocheng YU Xiaokang LI Xiaoqiao DONG Xiaoyan XU Zhihong LI Ru HUANG Ming LI Key Laboratory of Microelectronic Devices and Circuits(MOE) Institute of MicroelectronicsPeking University National Key Laboratory of Science and Technology on Micro/Nano Fabrication Peking University Faculty of Information Technology Beijing University of Technology

Dear editor,Recently, the integration of photosensitive material and electronic nanodevice has been the center of attention with Internet of things (IoT)technology development [1–3]. The immobilization of such photoactive molecules on the semiconductor surface was necessarily adopted to employ their photoelectric characteristics which can be observed in the solution. Porphyrin-based hybrid transistors have emerged as promising candidates for photonic sensing application due to the

关键词： A photomemory by selective-assembling hybrid porphyrin-silicon nanowire field-effect transistor

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