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Physical investigation of subthreshold swing degradation behavior in negative capacitance FET

Science China(Information Sciences) 2022年第6期65卷 241-246页

作者： Mengxuan YANG Qianqian HUANG Kaifeng WANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Power consumption has become one of the bottlenecks limiting the future development of integrated circuits. Tunnel FETs(TFETs) and negative capacitance FETs(NCFETs) can break the subthreshold swing limitation(60 mV/dec at room temperature) of conventional metal-oxide-semiconductor field-effect transistor(MOSFET) to reduce the operating voltage and thus power consumption. However, induced by the band-to-band tunneling mechanism, TFETs have a subthreshold swing degradation issue and relatively low ON current. Although NCFETs with ferroelectric/dielectric gate stack can theoretically maintain a high ON current comparable to conventional MOSFET, the physical origin of sub-60 SS is controversial and the mechanism of switching behavior in NCFET is still not clear. In this work, by experimentally investigating the whole negative differential capacitance process and its gate voltage amplification coefficient, an intrinsic issue of SS degradation with increased gate voltage is also found in NCFET for the first time. Based on the physical investigation and simulation results, it is shown that the intrinsic SS degradation in NCFET is resulting from the instant dielectric polarization response. Both the decrease of dielectric thickness and the increase of dielectric constant may lead to the severer SS degradation, which is not favorable for scaled NCFETs.

关键词： ferroelectric negative differential capacitance effect polarization low power voltage amplification

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Experimental investigation of the gate voltage range of negative differential capacitance in ferroelectric transistors

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Science China(Information Sciences) 2022年第6期65卷 277-278页

作者： Mengxuan YANG Qianqian HUANG Chang SU Liang CHEN Yangyuan WANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of MicroelectronicsPeking University Beijing Laboratory of Future IC Technology and Science Peking University

Dear editor,Recently, ferroelectric(FE)-based negative capacitance FET(NCFET) with ferroelectric/dielectric(FE/DE) gate stack has attracted extensive attention due to its capability of sub-60 mV/dec subthreshold swing... 详细信息

关键词： Ferroelectric Negative differential capacitance effect Polarization Low power Subthreshold swing

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Layout dependence of total-ionizing-dose response in 65-nm bulk Si pMOSFET

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Science China(Information Sciences) 2021年第2期64卷 271-272页

作者： Zhexuan REN Xia AN Gensong LI Xing ZHANG Ru HUANG Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Strain technology has become a common solution in the semiconductor manufacturing industry since 90-nm technology node to overcome the severe carrier mobility degradation of nanoscale microelectronic devices [1]. Since layout may affect the stress distribution, layout dependent effect(LDE)becomes a serious issue in advanced technology nodes.

关键词： Information Systems and Communication Service

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CMN: a co-designed neural architecture search for efficient computing-in-memory-based mixture-of-experts

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Science China(Information Sciences) 2024年第10期67卷 100-114页

作者： Shihao HAN Sishuo LIU Shucheng DU Mingzi LI Zijian YE Xiaoxin XU Yi LI Zhongrui WANG Dashan SHANG Department of Electrical and Electronic Engineering The University of Hong Kong ACCESS-AI Chip Center for Emerging Smart Systems InnoHK Centers Key Lab of Fabrication Technologies for Integrated Circuits Chinese Academy of Sciences Laboratory of Microelectronics Devices and Integrated Technology Institute of MicroelectronicsChinese Academy of Sciences University of Chinese Academy of Sciences School of Microelectronics Southern University of Science and Technology

Artificial intelligence(AI) has experienced substantial advancements recently, notably with the advent of large-scale language models(LLMs) employing mixture-of-experts(MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory(CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert's location,quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search(NAS) framework, CIM-based MoE NAS(CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM(SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67×(43.10×) energy savings,175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

关键词： mixture-of-experts computing-in-memory neural architecture search resistive random-access memory static random-access memory

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Low Power EEPROM Designed for Sensor Interface Circuit

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Chinese Journal of Electronics 2023年第4期21卷 642-644页

作者： Xiangyun MENG Sen YANG Zhongjian CHEN Wengao LU Yacong ZHANG Jingqing HUANG Haojiong LI Weiguo SU Song LI Department of Microelectronics Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China

EEPROM is an important part for interface circuit of sensor. It saves the calibration data and parameter setting data by non-volatile storage. A new low- power Erasable and electrically programmable read only memory (EEPROM) circuit for sensor interface circuit is introduced in this paper. The data stored in EEPROM can be reloaded automatically by the power-on-reset technique when the power is on. The module consumes power only during power-on-reset and data changing by status optimization and low-power design. This EEPROM circuit has been used in a MEMS accelerometer readout circuit verified by 0.35.μm CMOS EEPROM process. The results are satisfying in that the module can write and store 25bit data and automatically reloads data within 0.1.μs after power-on and then turns to low power mode.

关键词： Micromechanical devices Accelerometers Nonvolatile memory EPROM Calibration Research and development Optimization

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A centripetal collection image sensor(CCIS) based on back gate modulation achieving 1T submicron pixel

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Science China(Information Sciences) 2022年第4期65卷 282-284页

作者： Liqiao LIU Guihai YU Gang DU Xiaoyan LIU Key Laboratory of Microelectronic Devices and Circuits Institute of MicroelectronicsPeking University

Dear editor,Image sensors have been rapidly developed for decades and widely used in many different fields [1, 2]. To achieve high resolution, the pixel size has been scaled down to 1 μm for mass production [3]. Nevertheless, the pixel size has to be further reduced to meet the growing demand for higher resolution. In CMOS image sensor(CIS), the pixel is composed of a photodiode, reset transistor,

关键词： Image sensor submicron pixel back gate modulation pixel crosstalk Silicon on insulator

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High Frame Rate High Linearity Low Power DROIC for 30μm-Pitch Cryogenic Infrared FPAs 14

High Frame Rate High Linearity Low Power DROIC for 30μm-Pit...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Gu, Yuting Liu, Fengqing Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a pixel circuit with high frame rate, high linearity, and low power consumption. This pixel circuit is applied in a digital readout integrated circuit (DROIC) of 320×256 infrared focal plane array(IRFPA). The proposed single slope ADC is deployed in the proposed pixel circuit, which improves linearity and power consumption of the DROIC. The proposed pixel circuit is fabricated using 180nm 1P5M CMOS process with 30μm pixel pitch. Pixel power consumption is 406nW. Frame rate of the proposed DROIC is 1KHz. Nonlinearity of the quantization is lower than 0.8%. © 2021 IEEE.

关键词： Electric power utilization

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Low Power Readout Integrated Circuit with PFM-based ADCs Employing Residue Quantization for Uncooled Infrared Imagers 14

Low Power Readout Integrated Circuit with PFM-based ADCs Emp...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Zhou, Ye Yu, Shanzhe Lu, Wengao Yu, Dunshan Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

This paper presents a low power readout integrated circuit (ROIC) with 12-bit two-stage column-wise ADCs for 25μm-pitch 640×480 silicon diode uncooled infrared imagers. A novel two-stage column-wise ADC composed of a pulse frequency modulation (PFM)-based ADC for coarse conversion and a single-slope ADC for fine conversion is proposed. The proposed ADC meets the requirements for power budget, conversion rate, and linearity performance in column-wise ADC application for uncooled infrared imagers. The PFM-based ADC adopts a passive integrator and an optimized comparator structure to reduce static power consumption. The ROIC is designed in standard 0.18μm 1P5M CMOS process. Simulation shows that the SNR and nonlinearity is 74dB and 0.12%, respectively. Power consumption of the ROIC is 54mW and each column ADC consumes only 10μW. © 2021 IEEE.

关键词： Budget control

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A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm Pitch 320 ×256 LWIR FPAs 14

A 16-bit Pixel-level ADC Based on Ring Oscillator for 30μm ...

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14th IEEE International Conference on ASIC, ASICON 2021

作者： Niu, Yuze Liu, Bingxin Kong, Jiaqi Zhou, Fei Yu, Shanzhe Lu, Wengao Zhang, Yacong Chen, Zhongjian Peking University Key Laboratory of Microelectronic Devices and Circuits Department of Microelectronics China

ISBN: (纸本)9781665411493

A low-power and high-dynamic range ADC-based 320×256 size digital readout integrated circuit for infrared focal plane arrays is proposed in this paper. Compared with the traditional structure, the proposed pixel-level ADC structure based on ring oscillator can achieve higher dynamic range and lower power consumption. The design is based on 0.18μm 1P5M CMOS process, and the pixel circuit pitch is 30μm. The simulation results show that the average power consumption of the proposed single pixel-level ADC is 1.36μW. The charge handling capacity of the pixel is 2.8Ge-;the dynamic range is 96.32dB, and the non-linearity is 0.76%. © 2021 IEEE.

关键词： Pixels

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A Depletion-enhanced N Layers Stacked LDMOS 3

A Depletion-enhanced N Layers Stacked LDMOS

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3rd International Symposium on Semiconductor and Electronic Technology, ISSET 2024

作者： Li, Qi Liang, Lanyi Guan, Li Dang, Tianbao Huang, Hong Chen, Yonghe Guilin University of Electronic Technology Guangxi Key Laboratory of Precision Navigation Technology and Application Guilin541004 China Key Laboratory of Microelectronic Devices and Integrated Circuits Navigation Department of Guangxi Zhuang Autonomous Region Guilin541004 China

ISBN: (纸本)9798350390285

With the development of power integrated circuits, LDMOS devices assume a significant role in power device applications due to their elevated input impedance and enhanced conversion rate. Nonetheless, a contradictory relationship exists between the breakdown voltage and specific on-resistance in power LDMOS devices. Consequently, an n-layer stacked lateral double-diffused metal-oxide-semi conductor transistor(SLDMOS) is proposed, in which numerous MOS cells are stacked under the same chip area. The on-state resistance (R_on) of the n layers S-LDMOS is decreased significantly because of the vertical parallel connection, also the interference among devices is weakened through electrode interconnection isolated by oxidation layer. Multiple drift regions are formed by alternate epitaxy N-layer (drift region) and P-layer (substrate), and each drift region is depleted by the top and bottom P substrates, leading to a much lower R_on. The lightly-doped substrate and N/P top region are used to improve the breakdown characteristics, and the floating P layers are introduced to enhance the depletion effect in drift regions and decrease device thicknesses. By optimizing the configuration, a balanced trade-off is obtained. The simulation results indicate that compared with the traditional LDMOS, the 2 layers S-LDMOS exhibits a BV of 356 V and a specific on resistance (R_on,sp) of 13.56 mΩċ cm2, an improvement of 26.2 % and 71.6%, respectively. And the R_on, sp of n layers S-LDMOS will be reduced to less than 1/n of C-LDMOS further. © 2024 IEEE.

关键词： Power integrated circuits

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