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International Conference on Solid-State and Integrated Circuit Technology

作者： Yiqing Li Qianqian Huang Mengxuan Yang Ting Li Zhixuan Wang Weihai Bu Jin Kang Wenbo Wang Shengdong Zhang Ru Huang School of Electronic and Computer Engineering Peking University Shenzhen China Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Semiconductor Technology Innovation Center (Beijing) Beijing China

ISBN: (数字)9781728162355

ISBN: (纸本)9781728162362

A novel Si-based tunnel field effect transistor (TFET) with self-aligned dopant-segregated Schottky (DSS) source and underlap-drain is proposed and manufactured based on standard CMOS process. Asymmetric sidewall structures are introduced and manufactured for the process of self-aligned DSS source/drain. In the proposed device, DSS structure is able to optimize the source junction of devices without introducing ambipolar effect. The fabricated device improves the on-current by about two orders of magnitude compared with the conventional TFET without DSS structure, and suppress the ambipolar current over two orders of magnitude compared with the DSS-TFET without asymmetric sidewall structures. The experimental results demonstrate the great potential of the device for ultra-low power IOT applications.

关键词： TFETs Silicides Standards Internet of Things Logic gates CMOS process Junctions

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A Novel Electrical Isolation Solution for Tunnel FET Integration

A Novel Electrical Isolation Solution for Tunnel FET Integra...

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China Semiconductor Technology International Conference (CSTIC)

作者： Ting Li Qianqian Huang Le Ye Yuan Zhong Mengxuan Yang Yiqing Li Yimei Li Zhongxin Liang Ru Huang School of Electronic Information Engineering Anhui University Hefei China Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China Peking University Information Technology Institute (Tianjin Binhai)

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, for bulk tunnel field-effect transistors (TFET), the electrical isolation solutions between neighboring devices for TFET integration are investigated. To suppress the leakage current of the P-type doped regions through the P-type substrate, a new effective isolation method is proposed and verified via simulation. The simulation shows the leakage current can be reduced from 10 -5 A/μm to 10 -13 A/μm. The solution is beneficial for TFETs to keep its advantages for ultra-low power applications such as implantable medical devices and Internet of Things.

关键词： TFETs Medical devices Leakage currents Low-power electronics Internet of Things Substrates

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A 12-GHz All-Digital Calibration-Free FMCW Signal Generator Based on a Retiming Fractional Frequency Divider

A 12-GHz All-Digital Calibration-Free FMCW Signal Generator ...

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IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Zhengkun Shen Heyi Li Haoyun Jiang Zherui Zhang Junhua Liu Huailin Liao Key Laboratory of Microelectronic Devices and Circuits (MOE) Institute of Microelectronics Peking University Beijing China

ISBN: (数字)9781728151069

ISBN: (纸本)9781728151076

A 12-GHz all-digital calibration-free frequency-modulated continuous-wave (FMCW) signal generator is presented in this paper based on a retiming fractional frequency divider (FFD). Instead of modulating a multi-modulus divider (MMD) by a ΔΣ modulator, a fractional divider is utilized to release the narrow loop bandwidth limitation and achieve better phase noise without active noise cancellation techniques. Thus, the FMCW signal generator can achieve low root-mean-square (RMS) frequency error under a fast chirp slop. A calibration-free retiming FFD architecture which is not sensitive to process, voltage and temperature (PVT) variations is proposed to avoid complex and slow calibration process. Implemented in 40-nm CMOS, the generator consumes 33.8 mW power and 0.32 mm 2 chip area. Measurement results show that the generator achieves 78 MHz/μs maximum chirp slope and 6.0 kHz RMS frequency error when 300 MHz frequency is swept in 2 ms. The phase noise from 12 GHz carrier is -113.6 dBc/Hz at 1 MHz offset.

关键词： Chirp Generators Frequency conversion Phase noise Bandwidth Linearity Frequency modulation

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In-memory search with learning to hash based on resistive memory for recommendation acceleration

npj Unconventional Computing

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npj Unconventional Computing 2024年第1期1卷 1-9页

作者： Fei Wang Woyu Zhang Zhi Li Rui Bao Xiaoxin Xu Chunmeng Dou Dashan Shang Ning Lin Zhongrui Wang Key Lab of Fabrication Technologies for Integrated Circuits Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China Key Laboratory of Microelectronic Devices and Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing 100029 China University of Chinese Academy of Sciences Beijing 100049 China Department of Electrical and Engineering the University of Hong Kong Hong Kong China ACCESS - AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong China School of Microelectronics Southern University of Science and Technology Shenzhen 518055 China

Similarity search is essential in current artificial intelligence applications and widely utilized in various fields, such as recommender systems. However, the exponential growth of data poses significant challenges in search time and energy consumption on traditional digital hardware. Here, we propose a software-hardware co-optimization to address these challenges. On the software side, we employ a learning-to-hash method for vector encoding and achieve an approximate nearest neighbor search by calculating Hamming distance, thereby reducing computational complexity. On the hardware side, we leverage the resistance random-access memory crossbar array to implement the hash encoding process and the content-addressable memory with an in-memory computing paradigm to lower the energy consumption during searches. Simulations on the MovieLens dataset demonstrate that the implementation achieves comparable accuracy to software and reduces energy consumption by 30-fold compared to traditional digital systems. These results provide insight into the development of energy-efficient in-memory search systems for edge computing.

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Random resistive memory-based deep extreme point learning machine for unified visual processing

arXiv

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arXiv 2023年

作者： Wang, Shaocong Gao, Yizhao Li, Yi Zhang, Woyu Yu, Yifei Wang, Bo Lin, Ning Chen, Hegan Zhang, Yue Jiang, Yang Wang, Dingchen Chen, Jia Dai, Peng Jiang, Hao Lin, Peng Zhang, Xumeng Qi, Xiaojuan Xu, Xiaoxin So, Hayden Wang, Zhongrui Shang, Dashan Liu, Qi Cheng, Kwang-Ting Liu, Ming Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Key Laboratory of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China ACCESS - AI Chip Center for Emerging Smart Systems InnoHK Centers Hong Kong Science Park Hong Kong University of Chinese Academy of Sciences Beijing100049 China Frontier Institute of Chip and System Fudan University Shanghai200433 China College of Computer Science and Technology Zhejiang University Zhejiang310027 China Department of Electronic and Computer Engineering The Hong Kong University of Science and Technology Hong Kong

Visual sensors, including 3D LiDAR, neuromorphic DVS sensors, and conventional frame cameras, are increasingly integrated into edge-side intelligent machines. Realizing intensive multi-sensory data analysis directly on edge intelligent machines is crucial for numerous emerging edge applications, such as augmented and virtual reality and unmanned aerial vehicles, which necessitates unified data representation, unprecedented hardware energy efficiency and rapid model training. However, multi-sensory data are intrinsically heterogeneous, causing significant complexity in the system development for edge-side intelligent machines. In addition, the performance of conventional digital hardware is limited by the physically separated processing and memory units, known as the von Neumann bottleneck, and the physical limit of transistor scaling, which contributes to the slowdown of Moore's law. These limitations are further intensified by the tedious training of models with ever-increasing sizes. In this study, we propose a novel hardware-software co-design, random resistive memory-based deep extreme point learning machine (DEPLM), that offers efficient unified point set analysis. Data-wise, the multi-sensory data are unified as point sets and can be processed universally. Software-wise, most weights of deep extreme point learning machines are exempted from training, which significantly reduce training complexity. Hardware-wise, nanoscale resistive memory not only enables collocation of memory and processing, mitigating the von Neumann bottleneck and the slowdown of Moore's law, but also leverages the inherent programming stochasticity for generating the random and sparse weights of the DEPLM, which also lessens the impact of read noise. We demonstrate the system's versatility across various data modalities and two different learning tasks. Compared to a conventional digital hardware-based system, our co-design system achieves 5.90×, 21.04×, and 15.79× energy efficiency improv

关键词： Cost reduction

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Implementation of Graph Convolution Network Based on Analog Rram

Implementation of Graph Convolution Network Based on Analog ...

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China Semiconductor Technology International Conference (CSTIC)

作者： Daqin Chen Zongwei Wang Shengyu Bao Yimao Cai Ru Huang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China Frontiers science center for nano-optoelectronics Peking University Beijing P. R. China

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, the implementation of Graph Convolutional Network (GCN) based on resistive switching memory is demonstrated through simulation. After training, the RRAM-based GCN can process a semi-supervised graph classification task. Further, the impacts of read noises and circuit bit-precision on the performance of GCN are analyzed. Results show the proposed GCN can reach high accuracy when bit-precisions; 4-bit. Moreover, read noise can severely affect accuracy.

关键词： Training Knowledge engineering Convolution Switches Task analysis Integrated circuit modeling Analog-digital conversion

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Impact of Circuit Limit and Device Noise on RRAM Based Conditional Generative Adversarial Network

Impact of Circuit Limit and Device Noise on RRAM Based Condi...

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China Semiconductor Technology International Conference (CSTIC)

作者： Shengyu Bao Zongwei Wang Tianyi Liu Daqin Chen Yimao Cai Ru Huang Institute of Microelectronics Peking University Beijing China Key Laboratory of Microelectronic Devices and Circuits Peking University Beijing China Frontiers science center for nano-optoelectronics Peking University Beijing P. R. China

ISBN: (数字)9781728165585

ISBN: (纸本)9781728165592

In this work, a Conditional Generative Adversarial Network (CGAN) [1] is demonstrated based on the Resistive Random Access Memory (RRAM). During training, the read noise of RRAM is utilized as a random bias source to enrich the diversity of the generator in CGAN. Further, we evaluate the impact of both read noise (RRAM as weight storage cell) and the resolution of the AD/DA circuit on the performance of CGAN through a comprehensive simulation.

关键词： Training Performance evaluation Random access memory Semisupervised learning Generative adversarial networks Generators Integrated circuit modeling

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Fully Integrated Point-of-Care Complete Blood Count Using Multi-Frame Morphology Analysis

SSRN

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SSRN 2022年

作者： Zhang, Wenchang Li, Ya Chen, Bing Zhang, Yuan Du, Ziqiang Xiang, Feibin Hu, Yu Meng, Xiaochen Shang, Chunliang Liang, Shengfa Yang, Xiaonan Guan, Weihua Key Lab of Microelectronic Devices & Integrated Technology Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China Department of Gastroenterology The First Affiliated Hospital of Zhengzhou University Zhengzhou450052 China Key Clinical Laboratory of Henan Province Department of Clinical Laboratory The First Affiliated Hospital of Zhengzhou University Zhengzhou450052 China School of Information Engineering Zhengzhou University Zhengzhou450001 China Key Laboratory of the Ministry of Education for Optoelectronic Measurement Technology and Instrument Beijing Information Science & Technology University Beijing100192 China Department of Obstetrics and Gynecology Peking University Third Hospital Beijing100191 China Department of Electrical Engineering Pennsylvania State University University Park16802 United States Department of Biomedical Engineering Pennsylvania State University University Park16802 United States

Point-of-care testing (POCT) of complete blood count (CBC) is an emerging approach that allows laypersons to identify and count whole blood cells through simple manipulation. To date, POCTs for CBC were mainly achieved by "stationary" images through blood smears or single-laity arranged cells in the microwell, making it difficult to obtain statistically sufficient numbers of cells. In this work, we present a fully integrated POCT device solely using "in-flow" imaging of 3 μL fingertip whole blood for improved identification and counting accuracy of CBC analysis. A miniaturized magnetic stirring module was integrated to maintain the temporal stability of cell concentration. A relatively high throughput (~ 8,000 cells/min) with a 30-fold dilution ratio of whole blood can be tested for as long as 1 hour to examine sufficient numbers of cells, and the subclass cell concentration keeps constant. To improve the identification accuracy, multi-frame "in-flow" imaging was used to track the cell motion trails with multi-angle morphology analysis. This proof-of-concept was then validated with healthy whole blood samples and 75 cases of clinical patients with abnormal concentrations of red blood cells (RBCs), white blood cells (WBCs), and platelets (PLT). The average precision (AP) value of WBCs identification was improved from 0.8622 to 0.9934. And the high fitting degrees (> 0.98) between our POCT device and the commercial clinical equipment indicated good agreement. This POCT device is user-friendly and cost-effective, making it a potential tool for diagnosing abnormal blood cell morphology or concentration in the field setting. © 2022, The Authors. All rights reserved.

关键词： Cells

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Low Voltage Dual-Modulus Frequency Divider Based on Extended True Single-Phase Clock Logic

Low Voltage Dual-Modulus Frequency Divider Based on Extended...

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2018 IEEE International Conference on Electron devices and Solid State circuits, EDSSC 2018

作者： Wang, Wanlu Jia, Song Wang, Ziyi Pan, Tao Wang, Yuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing100871 China

ISBN: (纸本)9781538662342

Two low voltage dual-modulus frequency divider based on extended true single-phase clock (E-TSPC) logic are proposed. By reducing the number of serial transistors from VDD to GND, the proposed designs can effectively work at low voltage. Simulation results in SMIC 40nm technology show that the presented design I has better power and speed performance with lower supply voltage. Compared to the referenced designs, the presented design II can work at the lowest supply voltage with little loss of performance. © 2018 IEEE.

关键词： Computer circuits

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Design of low-power high-speed dual-modulus frequency divider with improved MOS current mode logic

Design of low-power high-speed dual-modulus frequency divide...

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2018 IEEE International Conference on Electron devices and Solid State circuits, EDSSC 2018

作者： Wang, Wanlu Jia, Song Pan, Tao Wang, Yuan Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University Beijing100871 China

ISBN: (纸本)9781538662342

One design technique that aims to reduce power consumption of MOS current mode logic dual-modulus frequency divider is presented in this paper. With combinational logic transferred the proposed scheme can obtain high working frequency. By merging the first master latches of CML DFFs, the simplified structure can achieve lower power consumption. Circuit simulation of the proposed structure in 28nm CMOS technology shows a 21% reduction of power consumption over conventional scheme is achieved at frequency of 56GHz. © 2018 IEEE.

关键词： Electric power utilization

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